7

FN6230.2

March 1, 2011

The maximum power dissipation allowed in a package is

determined according to Equation 1.

where:

•

Approximate Power Dissipation

where:

N is the number of comparators in the chip

(1 for ISL55141, 2 for ISL55142 and 4 for ISL55143).

(f) is the operating frequency.

CL is the load capacitor.

The power dissipation calculated from the above formula

may have an error of ±20 to 25%.

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the loads.

Power also depends on the number of channels changing

state and frequency of operation. The extent of continuous

active pattern generation/reception will greatly affect

dissipation requirements.

The user should evaluate various heat sink/cooling options

in order to control the ambient temperature part of the

equation. This is especially true if the user’s applications

require continuous, high-speed operation.

Note: The reader is cautioned against assuming the same

level of thermal performance in actual applications. A careful

inspection of conditions in your application should be

conducted.

Power Supply Information

Circuit design must always take into account the internal

EOS/ESD protection structure of the device.

Important Note: The QFN package metal plane is used

for heat sinking of the device. It is electrically connected

ground, the thermal pad can be connected to ground.

other power planes.

Power Supply Sequencing

The ISL55141, ISL55142, ISL55143 reference every supply

In cases where inputs may exceed voltage rails during

power-up, series resistance should be employed to

safeguard EOS to the ESD protection diodes.

P

DMAX

T

Θ

JA

---------------------------------------------

=

(EQ. 1)

OPTIONAL PROTECTION

DIODE

OPTIONAL PROTECTION

DIODE

ISL55141, ISL55142, ISL55143