Technical Note

6/16

BU9888FV-W

www.rohm.com

2011.01 - Rev.A

© 2011 ROHM Co., Ltd. All rights reserved.

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Timing chart

1. Read cycle (READ)

Fig.25

Read cycle

(※1) Start bit

When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized

as a start bit, and the following operation is started. This is common to all the commands to described hereafter.

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When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,

in sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC

has an address auto increment function valid only at read command. This is the function where after the above read

execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto

increment, keep CS at “H”.

2. Write cycle (WRITE)

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In this command, input 16bit data (D15～D0) are written to designated addresses (A7~A0). The actual write starts by the

fall of CS of D0 taken SK clock. When STATUS is not detected, (CS=”L” fixed) Max. 2ms in conformity with tE/W, and

when STATUS is detected (CS=”H”), all commands are not accepted for areas where “L” ( BUSY ) is output from D0,

therefore, do not input any command.

Fig.26

Write cycle

(※2）Next address data(Auto increment function)

（※1）

（※2）

High-Z

0

A0

28

D0

27

D15

12

D14

D15 D14

D1

A1

0

12

4

1

1

A7

A6

CS

SK

DI

DO

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tCS

High-Z

READY

BUSY

tE/W

CS

SK

DI

DO

12

4

11

A1

A0

0

STATUS

12

27

D0

D1

D15 D14

1A7

A6

1

tSV

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