DAC1008D650 datasheet(11/98 Pages) NXP

номер детали	DAC1008D650

подробное описание детали	Dual 10-bit DAC; up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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DAC1008D650

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 17 December 2010

11 of 98

NXP Semiconductors

DAC1008D650

2

×, 4× or 8× interpolating DAC with JESD204A

[1]

D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2]

Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It

reflects the delay required by DAC1008D650 to lock to a JESD204A stream. It supposes that the TX is already transmitting

K28.5 characters in error-free conditions.

[3]

CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80

Ω and 120 Ω (see

Figure 15) should be connected across the pins.

[4]

|V

gpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance

and the inductance between the receiver and the driver circuit ground voltage.

[5]

Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50 Ω (see Figure 4).

[6]

SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80

Ω

and 120

Ω.

[7]

IMD3 rejection with

−6 dBFS/tone.

10. Application information

10.1 General description

The DAC1008D650 is a dual 10-bit DAC operating up to 650 Msps. With a maximum input

data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the

DAC1008D650 allows more flexibility for wide bandwidth and multi-carrier systems.

Combined with its quadrature modulator and 32-bit NCO, the DAC1008D650 simplifies

the frequency selection of the system. This is also possible because of the 2

×, 4× or 8×

interpolation filters which remove undesired images.

DAC1008D650 supports the following JESD204A key features:

• 10-bit/8-bit decoding

• Code group synchronization

• inter-lane alignment

• 1+x14 +x15 scrambling polynomial

• Character replacement

• TX/RX synchronization management via SYNC signals

• Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device

DAC1008D650 can be interfaced with any logic device that features high-speed SERDES

functionality. This macro is now widely available in FPGA from different vendors.

Standalone SERDES ICs can also be used.

To enhance the intrinsic board layout simplification of the JESD204A standard, NXP

includes polarity swapping for each of the lanes and additionally offers lane swapping.

Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.

NSD

noise spectral density

fs =640 Msps;

4

× interpolation;

fo = 133 MHz at 0 dBFS

I-

−145

-

dBm/Hz

Table 5.

Characteristics …continued

VDDA(1V8) =VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = −40 °C to

+85

°C; typical values measured at V

DDA(1V8) =VDDD =1.8 V; VDDA(3V3) =3.3 V; Tamb =+25 °C; RL =50 Ω; IO(fs) =20mA;

maximum sample rate; PLL off unless otherwise specified.

Symbol

Parameter

Conditions

Test[1]

Min

Typ

Max

Unit

Аналогичный номер детали - DAC1008D650

производитель	номер детали	датащи	подробное описание детали
NXP Semiconductors	DAC1008D650	2Mb / 98P	Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 1-1 October 2010
Renesas Technology Corp	DAC1008D650	631Kb / 96P	Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface 2 July 2012
NXP Semiconductors	DAC1008D650HN	2Mb / 98P	Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 1-1 October 2010
Renesas Technology Corp	DAC1008D650HN	631Kb / 96P	Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface 2 July 2012

More results

Аналогичное описание - DAC1008D650

производитель	номер детали	датащи	подробное описание детали
NXP Semiconductors	DAC1008D650	2Mb / 98P	Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 1-1 October 2010
	DAC1208D650	573Kb / 98P	Dual 12-bit DAC; up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 2-14 December 2010
	DAC1008D750	2Mb / 99P	Dual 10-bit DAC up to 750 Msps 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 01-4 October 2010
	DAC1208D750	571Kb / 98P	Dual 12-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 2-6 December 2010
	DAC1408D750	2Mb / 98P	Dual 14-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface Rev. 2-2 December 2010
	DAC1008D750	564Kb / 99P	Dual 10-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating Rev. 2-5 January 2011
Renesas Technology Corp	DAC1008D650	631Kb / 96P	Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface 2 July 2012
NXP Semiconductors	DAC1405D750	324Kb / 43P	Dual 14-bit DAC, up to 750 Msps; 4횞 and 8횞 interpolating Rev. 01-10 March 2010
NXP Semiconductors	DAC1408D650_1011	2Mb / 98P	Dual 14-bit DAC; up to 650 Msps; 2?? 4??or 8??interpolating with JESD204A interface Rev. 4-26 November 2010
Integrated Device Techn...	DAC1408D650	689Kb / 96P	Dual 14-bit DAC; up to 650 Msps; 2?? 4??or 8??interpolating with JESD204A interface

More results

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