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FM25L16B-DG датащи(PDF) 8 Page - Ramtron International Corporation

номер детали FM25L16B-DG
подробное описание детали  16Kb Serial 3V F-RAM Memory
Download  14 Pages
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производитель  RAMTRON [Ramtron International Corporation]
домашняя страница  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25L16B-DG датащи(HTML) 8 Page - Ramtron International Corporation

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FM25L16B - 16Kb 3V SPI F-RAM
Rev. 1.3
Mar. 2011
Page 8 of 14
Figure 9. Memory Write (WREN not shown)
Figure 10. Memory Read
Endurance
The FM25L16B devices are capable of being
accessed at least 10
14 times, reads or writes. An F-
RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A10-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 256 rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
(MHz)
Endurance
Cycles/sec.
Endurance
Cycles/year
Years to Reach
Limit
20
37,310
1.18 x 10
12
85.1
10
18,660
5.88 x 10
11
170.2
5
9,330
2.94 x 10
11
340.3
0
1
2
3
4567
0
1
2
34
5
6
4567
0
1
2
34567
op-code
0
0
0
0
0
0
1
MSB
11-bit Address
XX
X
X
X
10
9
321
0
76
54
3
2
10
LSB
MSB
LSB
CS
SCK
SI
SO
Data
1
0
1
2
3
4
567
0
1
2
34
5
4
567
0
1
2
34
5
6
7
op-code
0
0
0
0
0
0
1
0
MSB
11-bit Address
X
X
XX
X
10
3
2
1
0
76
54
321
0
LSB MSB
LSB
CS
SCK
SI
SO
Data
9
6


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