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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CSD96370Q5M_1110 датащи(PDF) 5 Page - Texas Instruments |
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CSD96370Q5M_1110 датащи(HTML) 5 Page - Texas Instruments |
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5 / 19 page  Shoot Through Control V DD V SW P GND B0433-01 PWM EN Boot V IN Boot_R Control FET Sync FET UVLO and ControlLogic V POR V DD UVLO 1.0V 1.0V GateDrive LatchZone T0487-01 CSD96370Q5M www.ti.com SLPS265C – NOVEMBER 2010 – REVISED OCTOBER 2011 Figure 3. Functional Block Diagram FUNCTIONAL DESCRIPTION POWERING CSD96370Q5M AND GATE DRIVERS An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive power for the MOSFETS. The gate driver IC is capable of supplying in excess of 4 Amps peak current into the MOSFET gates to achieve fast switching. A 1uF 10V X5R or higher ceramic capacitor is recommended to bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and BOOT_R pins. An optional RBOOT resistor which can be used to slow down the turn on speed of the Control FET and reduce voltage spikes on the Vsw node. A typical 1 Ω to 4.7Ω value is a compromise between switching loss and VSW spike amplitude. UVLO (Under Voltage Lock Out) The VDD supply is monitored for UVLO conditions and both Control FET and Sync FET gates are held low until adequate supply is available. An internal comparator evaluates the VDD voltage level and if VDD is greater than the Power On Reset threshold (VPOR) the gate driver becomes active. If VDD is less than the UVLO threshold, the gate driver is disabled and the internal MOSFET gates are actively driven low. At the rising edge of the VDD voltage, both Control FET and Sync FET gates will be actively held low during VDD transitions between 1.0V to VPOR. This region is referred to the Gate Drive Latch Zone (see Figure 4). In addition, at the falling edge of the VDD voltage, both Control FET and Sync FET gates are actively held low during the UVLO to 1.0V transition. The Power Stage CSD96370Q5M device must be powered up and Enabled before the PWM signal is applied. Figure 4. POR and UVLO Copyright © 2010–2011, Texas Instruments Incorporated 5 |
Аналогичный номер детали - CSD96370Q5M_1110 |
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Аналогичное описание - CSD96370Q5M_1110 |
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