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ADP1053DC-EVALZ датащи(PDF) 11 Page - Analog Devices

номер детали ADP1053DC-EVALZ
подробное описание детали  3-Channel Digital
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ADP1053DC-EVALZ датащи(HTML) 11 Page - Analog Devices

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Data Sheet
ADP1053
Rev. A | Page 11 of 84
Pin No.
Mnemonic
Description
19
SDA
PMBus/I2C Serial Data Input and Output (Open-Drain). This signal is referenced to AGND.
20
SCL
PMBus/I2C Serial Clock Input and Output (Open-Drain). This signal is referenced to AGND.
21
PSON_B
Power Supply On Input for Channel B. This signal is referenced to DGND.
22
CS
CS ADC Input and Fast Current Sense Input for Overcurrent Protection and Current Monitoring. This signal is
referenced to AGND.
23
CS1_B
CS1 ADC Input and Fast Current Sense Input for Channel B. This signal is referenced to AGND.
24
PGOOD_B
Power-Good Output (Open-Drain) for Channel B. This signal is referenced to AGND. This pin is controlled by the
PGOOD_B flag and is driven low when the flag is set. The PGOOD_B flag is set when the POWER_SUPPLY_B, UVP_B,
EEPROM_CRC, or SOFTSTART_FILTER_B flag is set. The ACSNS and OTW2 flags can also be programmed to be included.
25
CS2+_B
Noninverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should
be 1 V for optimal operation.
26
CS2−_B
Inverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should be 1 V
for optimal operation.
27
OVP_B
Overvoltage Protection Comparator Input for Channel B. This signal is referenced to PGND_B.
28
PGND_B
Reference Pin for Channel B Overvoltage Protection (OVP_B).
29
VS−_B
Inverting Input of the Voltage Sense ADC for Channel B Loop Control. There should be a low ohmic connection
to AGND.
30
VS+_B
Noninverting Input of the Voltage Sense ADC for Channel B Loop Control. This signal is referenced to VS−_B.
31
FLGI/SYNI
Flag Input/Synchronization Input. When this pin is programmed as a flag input, an external signal can be input
to generate a flag condition. The polarity is configurable. When this pin is programmed as a synchronization
input, the input signal is used as a reference for the internal PWM frequencies. This signal is referenced to AGND.
32
FLGO/SYNO
Flag Output/Synchronization Output. When this pin is programmed as a flag output, it can be used to indicate
the light load mode operation. The polarity is configurable. When this pin is programmed as a synchronization
output, it can be used as a frequency reference for synchronization. This signal is referenced to AGND.
33
RTD2
Thermistor ADC Input from Zone 2. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed
from this pin to AGND. This signal is referenced to AGND.
34
DGND
IC Digital Ground. Reference ground for the digital circuitry of the ADP1053. This pin should be star-connected to
AGND.
35
VCORE
Output of 2.5 V Regulator. Connect a 330 nF capacitor between this pin and DGND.
36
VDD
Positive Supply Voltage, 3.0 V to 3.6 V. This signal is referenced to AGND. Connect a 330 nF capacitor from VDD to
AGND.
37
AGND
IC Common Analog Ground. This pin should be star-connected to DGND.
38
RES
Resistor Input. This pin sets the internal voltage reference for the ADP1053. Connect a 10 kΩ resistor (±1%) from
RES to AGND. This signal is referenced to AGND.
39
ADD
PMBus/I2C Address Select Input. Connect a resistor from ADD to AGND (see the PMBus/I2C Address section). This
signal is referenced to AGND.
40
RTD1
Thermistor ADC Input from Zone 1. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed
from this pin to AGND. This signal is referenced to AGND.
EP
Exposed Pad
The exposed pad on the underside of the package should be soldered to AGND.


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