JITTER CHARACTERISTICS IN INPUT CLOCK MODE

CDC421Axxx

PhaseNoise

Analyzer

150 W

XIN1

XIN2

50 W

150 W

100pF

0.1pF

50 W

CDC421AXXX

Jitter characterization tests are performed using an LVCMOS input signal driving the CDC421Axxx device, as

Figure 2 illustrates.

Figure 2. Jitter Test Configuration for an LVTTL Input Driving CDC421Axxx

When the CDC421Axxx is referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33 MHz, and

35.4167 MHz, Table 1 to Table 7 list the measured SSB phase noise of all the outputs supported by the

CDC421Axxx device (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz)

from 100 Hz to 20 MHz from the carrier.

PARAMETER

MIN

TYP

MAX

UNIT

Phase noise at 100 Hz

–111

dBc/Hz

Phase noise at 1 kHz

–121

dBc/Hz

Phase noise at 10 kHz

–131

dBc/Hz

Phase noise at 100 kHz

–133

dBc/Hz

Phase noise at 1 MHz

–142

dBc/Hz

Phase noise at 10 MHz

–149

dBc/Hz

Phase noise at 20 MHz

–149

dBc/Hz

RMS jitter integrated from 12 kHz to 20 MHz

507

fs

Total jitter

35.33

ps

Deterministic jitter

11.54

ps

(1)

Phase noise specifications under following conditions: input frequency = 33.3333 MHz, output frequency = 100.00 MHz.

PARAMETER

MIN

TYP

MAX

UNIT

Phase noise at 100 Hz

–112

dBc/Hz

Phase noise at 1 kHz

–121

dBc/Hz

Phase noise at 10 kHz

–125

dBc/Hz

Phase noise at 100 kHz

–129

dBc/Hz

Phase noise at 1 MHz

–142

dBc/Hz

Phase noise at 10 MHz

–151

dBc/Hz

Phase noise at 20 MHz

–151

dBc/Hz

RMS jitter integrated from 12 kHz to 20 MHz

530

fs

Total jitter

30.39

ps

Deterministic jitter

11

ps

(1)

Phase noise specifications under following conditions: input frequency = 35.4167 MHz, output frequency = 106.25 MHz.

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