Si8900/1/2

10

Rev. 1.0

3. Functional Description

The Si8900/1/2 (Figure 4) are isolated monitoring ADCs that convert linear input signals into digital format and

transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a

microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC

conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires

ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port.

port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902).

The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series

gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user

to select an internal or external voltage reference, set the programmable gain amplifier (PGA), and select the ADC

MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or

continuously (Burst Mode). For more information, see "CNFG_0 Command Byte" on page 18.

Figure 4. Si8900/1/2 Block Diagrams

VDDA

GNDA

AIN0

AIN1

AIN2

VREF

      Si8900

ADC Subsystem

UART

PGA

MUX

10‐Bit

ADC

ISOLATION

Tx

Rx

GNDB

VDDB

All 

Blocks

Tx Data

VREF

State Machine/ 

User Registers

VDDA

GND1

AIN0

AIN1

AIN2

VREF

      Si8902

ADC Subsystem

SPI Port

PGA

MUX

10‐Bit

ADC

ISOLATION

SCK

GND2

VDDB

All 

Blocks

Tx Data

VREF

State Machine/ 

User Registers

SDI

SDO

VDDA

GNDA

AIN0

AIN1

AIN2

VREF

      Si8901

ADC Subsystem

SMBus/

PGA

MUX

10‐Bit

ADC

ISOLATION

SDA

SCL

GNDB

VDDB

All 

Blocks

Tx Data

VREF

State Machine/ 

User Registers

RSDA

RST

RST

RST

EN