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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TSB12LV32TPZEP датащи(PDF) 9 Page - Texas Instruments |
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TSB12LV32TPZEP датащи(HTML) 9 Page - Texas Instruments |
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9 / 105 page  Overview 2 SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP • 2K byte General Receive FIFO (GRF) Accessed Through Microcontroller Interface Supports Asynchronous and Isochronous Receive. • 2K byte Asynchronous Transmit FIFO (ATF) Accessed Through Microcontroller Interface Supports Asynchronous Transmissions. • Programmable Microcontroller Interface With 8-Bit or 16-Bit Data Bus, Multiple Modes of Operation Including Burst Mode, and Clock Frequency to 60 MHz • 8-Bit or 16-Bit Data-Mover Port (DM Port) Supports Isochronous, Asynchronous, and Asynchronous Streaming Transmit/Receive From an Unbuffered Port at a Clock Frequency of 25 MHz. • Backward Compatible With All TSB12LV31(GPLynx) Microcontroller and Data-Mover Functionality in Hardware • Two-Channel Support for Isochronous Receive to Unbuffered 8/16 Data-Mover Port • Four-Channel Support for Isochronous Transmit From Unbufferred 8/16 Bit Data-Mover Port • Single 3.3-V Supply Operation With 5-V Tolerance Using 5-V Bias Terminals • High Performance 100-Pin PZ Package 1.3 Functional Block Diagram MA[0:6] MD[0:15] BCLK Byte Stacker 8-/16-to-32 Bits 7 16 7 32 Address 7 Data 32 FIFO CFR Control IRF 32 CTL[0:1] Data Mover (DM) DMD[0:15] DM Control 16 Data- Mover Port 32 DM IT/AT ÷ 2 SCLK Microcontroller Interface MCA MCS Status 2K ATF 2K GRF 32 DM IR/AR ATF GRF DMCLK D[0:7] LREQ LPS LinkOn MRW ARF 32 ATF 32 Figure 1−1. TSB12LV32 Functional Block Diagram |
Аналогичный номер детали - TSB12LV32TPZEP |
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Аналогичное описание - TSB12LV32TPZEP |
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