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TLC5733AIPM датащи(PDF) 9 Page - Texas Instruments |
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TLC5733AIPM датащи(HTML) 9 Page - Texas Instruments |
9 / 23 page TLC5733A 20 MSPS 3CHANNEL ANALOGTODIGITAL CONVERTER WITH HIGHPRECISION CLAMP SLAS104B − JULY 1995 − REVISED FEBRUARY 2001 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) timing error of COMPOSITE SYNC The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 clocks wide (interval F). This function maintains the synchronization pattern when COMPOSITE SYNC is not present. summary of device operation with COMPOSITE SYNC This internal timing allows the TLC5733A to correctly position the clamp pulse when an external COMPOSITE SYNC input: • Is delayed with respect to the horizontal sync period • Is early with respect to the horizontal sync period • Is nonexistent during the horizontal sync period • Has falling edge noise spikes within the horizontal sync period The device operation is summarized as follows for these improper external clamp conditions: • Under all four conditions on EXTCLP, the internal clamp generation circuit generates a clamp pulse at the proper time after the horizontal sync period as shown in Figure 1. • The TLC5733A internal clamp circuit generates an internal clamp pulse each 1H time for the entire time interval that the COMPOSITE SYNC input is missing. 1H Missing COMPOSITE SYNC, therefore, Noise Gate is Not Generated B A C F D F E NTSC/PAL Counter Reset NTSC/PAL Counter at Max Count COMPOSITE SYNC Noise Gate 1 Noise Gate 2 Internal Clamp Pulse Figure 1. COMPOSITE SYNC and Internal Clamp Timing |
Аналогичный номер детали - TLC5733AIPM |
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Аналогичное описание - TLC5733AIPM |
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