TMS34094

ISA BUS INTERFACE

SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992

POST OFFICE BOX 1443

6

functional block diagram

Address Translation

Assync. Multiplexing Transceiver

Access

De-

code

Data

Flow

Control

Graphics

System

Interface

Local

Address

Decode

I/O

Registers

IOSEL

ISA Address

ISA Control

ISA Data

Host Address

BSEL

TMS34020

Memory Control

TMS34020

Host Port Control

LAD

memory mapped ISA interface to TMS34020 local memory

The memory mapped interface provides the option to map part or parts of the TMS34020 local memory into one

or more segments of the ISA host memory space. The memory map registers (MAP0–MAP3) (page 13), base

memory registers (BASE0–BASE3) (page 13), and map extension register (MAP0E) (page 8), in the TMS34094

are dedicated to memory mapped interface support. The MODECTL (page 7) register contains the configuration

bits for the memory mapped interface.

Each BASEn register contains the base address and size of a segment of ISA memory. The size of each

segment can be configured from 8 K-bytes to 4 M-bytes. Associated with each BASEn memory register is a

MAPn register which points to a location in TMS34020 local memory. When an ISA memory access falls within

one of the segments defined by BASE0–BASE3, the TMS34094 generates HA5–HA31 based on a combination

of the ISA address presented and the value in the corresponding MAP0–MAP3 register, and then initiates a host

access. Each window may be individually configured to respond as an 8-bit or 16-bit ISA memory mapped

device.

The map extension register, MAP0E, extends MAP0 to contain all the address bits required to specify a complete

host access address to the TMS34020. This will allow the ISA segment to be completely misaligned from the

TMS34020 segment when an access uses the TMS34020s autoincrement mode. The ISA host may transfer

up to 4 M-bytes of data without having to remap regardless of the alignment of the start address. The AI bit in

the MODECTL register must have the same value as the HPFW bit of the TMS34020’s HSTCTLH register, and

HLB0 and HLB1 (also HSTCTLH) must both be set to 0 for the TMS34020 to properly track host addresses in

autoincrement mode.

I/O mapped ISA interface to TMS34020 local memory

The I/O mapped interface presents a TMS34010-like interface between the ISA bus and the TMS34020 local

memory. Communication between the ISA bus and TMS34020 local memory is controlled by three registers

HADDRH, HADDRL, and HDATA (pages 11 and 12). HADDRH and HADDRL, in conjunction, hold a 28-bit

address pointing to a 16-bit quantity within TMS34020 local memory.