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UC1846-EP датащи(PDF) 5 Page - Texas Instruments

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номер детали UC1846-EP
подробное описание детали  CURRENT-MODE PWM CONTROLLER
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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UC1846-EP датащи(HTML) 5 Page - Texas Instruments

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DVPIN7
DVPIN4
UC1846-EP
CURRENT-MODE PWM CONTROLLER
SGLS329 – MAY 2006
Electrical Characteristics (continued)
T
A = –55°C to 125°C, VIN = 15 V, RT = 10 k, CT = 4.7 nF, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current-Sense Amplifier
Amplifier gain
VPIN3 = 0 V, Pin 1 open(2)(3)
2.5
2.75
3
V
Maximum differential input signal
Pin 1 open,(2) RL (pin 7) = 15 kW
1.1
1.2
V
(VPIN4 – VPIN3)
Input offset voltage
VPIN1 = 0.5 V, Pin 7 open(2)
5
25
mV
CMRR
VCM = 1 V to 12 V
60
83
dB
PSRR
VIN = 8 V to 40 V
60
84
dB
Input bias current
VPIN1 = 0.5 V, Pin 7 open(2)
–2.5
–10
µA
Input offset current
VPIN1 = 0.5 V, Pin 7 open(2)
0.08
1
µA
Input common-mode range
0
VIN – 3
V
Delay to outputs
TJ = 25°C(4)
200
500
ns
Current-Limit Adjust
Current-limit offset
VPIN3 = 0 V, VPIN4 = 0 V, Pin 7 open(2)
0.45
0.5
0.55
V
Input bias current
VPIN5 = VREF, VPIN6 = 0 V
–10
–30
µA
Shutdown Terminal
Threshold voltage
250
350
400
mV
Input voltage range
0
VIN
V
Minimum latching current (IPIN1)(5)
3
1.5
mA
Maximum nonlatching current (IPIN1)(6)
1.5
0.8
mA
Delay to outputs
TJ = 25°C(4)
300
600
ns
Output
Collector-emitter voltage
40
V
Collector leakage current
VC = 40 V
200
µA
ISINK = 20 mA
0.1
0.4
Output low level
V
ISINK = 100 mA
0.4
2.1
ISOURCE = 20 mA
13
13.5
Output high level
V
ISOURCE = 100 mA
12
13.5
Rise time
CL = 1 nF, TJ = 25°C(4)
50
300
ns
Fall time
CL = 1 nF, TJ = 25°C(4)
50
300
ns
Undervoltage Lockout
Start-up threshold
7.7
8
V
Threshold hysteresis
0.75
V
Total Standby Current
Supply current
17
21
mA
(2)
Parameter measured at trip point of latch with VPIN5 = VREF, VPIN6 = 0 V.
(3)
Amplifier gain defined as:
where VPIN4 = 0 to 1 V
(4)
These parameters, although specified over the recommended operating conditions, are not 100% tested in production.
(5)
Current into pin 1 is ensured to latch circuit in shutdown state.
(6)
Current into pin 1 is ensured not to latch circuit in shutdown state.
5
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