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SN74ACT7801 датащи(PDF) 5 Page - Texas Instruments |
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SN74ACT7801 датащи(HTML) 5 Page - Texas Instruments |
5 / 19 page SN74ACT7801 1024 × 18 CLOCKED FIRST IN, FIRST OUT MEMORY SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 functional description (continued) write clock (WRTCLK) Data is written into memory on a low-to-high transition of the write clock (WRTCLK) if the input-ready flag output (IR) and the write-enable control inputs (WRTEN1, WRTEN2) are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all data transfers into the FIFO. The IR flag output is also driven synchronously with respect to the WRTCLK signal. read enables (RDEN1, RDEN2) Both read enables (RDEN1, RDEN2) must be high before the rising edge of read clock (RDCLK) to read a word out of memory. The read enables are not used to read the first word stored in memory. read clock (RDCLK) Data is read out of memory on a low-to-high transition at the read-clock (RDCLK) input if the output-ready flag output (OR) and the output-enable (OE) and read-enable (RDEN1, RDEN2) control inputs are high. RDCLK is a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. The OR flag is also driven synchronously with respect to the RDCLK signal. define almost-full (DAF) The high-to-low transition of the define almost-full (DAF) input stores the binary value of data inputs D0 −D8 as the almost-full/almost-empty offset value (X). With DAF held low, a low pulse on the reset (RESET) input defines the almost-full/almost-empty flag (AF/AE) using X. output enable (OE) The data-out (Q0−Q17) outputs and the output-ready flag (OR) are in the high-impedance state when the output enable (OE) input is low. OE must be high before the rising edge of read clock (RDCLK) to read a word from memory. outputs data out (Q0 −Q17) The first data word to be loaded into the FIFO is moved to the data out (Q0 − Q17) register on the rising edge of the third read clock (RDCLK) pulse to occur after the first valid write. The read-enable (RDEN1, RDEN2) inputs do not affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, and the output-ready flag (OR) are high. input-ready flag (IR) The input-ready flag (IR) is high when the FIFO is not full and low when the device is full. During reset, the IR flag is driven low on the rising edge of the second write clock (WRTCLK) pulse. The IR flag is driven high on the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR is driven high on the second WRTCLK pulse after the first valid read. output-ready flag (OR) The output-ready flag (OR) is high when the FIFO is not empty and low when it is empty. During reset, the OR flag is set low on the rising edge of the third read clock (RDCLK) pulse. The OR flag is set high on the rising edge of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of the first RDCLK pulse after the last word is read. half-full status flag (HF) The half-full flag (HF) is high when the FIFO contains 513 or more words and is low when it contains 512 or less words. |
Аналогичный номер детали - SN74ACT7801 |
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Аналогичное описание - SN74ACT7801 |
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