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CXA3197R датащи(PDF) 6 Page - Sony Corporation |
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CXA3197R датащи(HTML) 6 Page - Sony Corporation |
6 / 30 page – 6 – CXA3197R Clock input. Use this pin when the clock is input at PECL level. At this time, leave Pin 19 open. CLKP/E and CLKN/E are complementary and should be used together. CLKP/E complementary input. Reset signal input. When multiple CXA3197R are operated at the same time in MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be matched. At this time, the reset signal is used; when the reset signal is at TTL level, Pin 22 is used and Pins 23 and 24 are left open. When the reset signal is at PECL level, Pins 23 and 24 are used and Pin 22 is left open. The reset signal polarity can be set by Pin 39 (R POLARITY). Leave the reset pin open when other modes are used. RESETP/E and RESETN/E are complementary and should be used together. CLKP/E PECL 20 I CLKN/E PECL 21 I RESET/T TTL 22 I RESETP/E PECL 23 I RESETN/E PECL 24 I DGND2 Single power supply: GND Dual power supply: –5V 25 DVCC1 DGND1 20 21 Function setting. Function setting. Function setting. C1 TTL 26 I C2 TTL 27 I C3 TTL 28 I 26 28 DVCC1 DGND1 27 1.5V DVCC1 DGND1 22 1.5V DVCC1 DGND1 23 24 Digital power supply. Pin No. Symbol Typical voltage level Equivalent circuit Description I/O |
Аналогичный номер детали - CXA3197R |
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Аналогичное описание - CXA3197R |
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