поискавой системы для электроныых деталей |
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74AUP1G56 датащи(PDF) 3 Page - Fairchild Semiconductor |
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74AUP1G56 датащи(HTML) 3 Page - Fairchild Semiconductor |
3 / 10 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AUP1G56 • Rev. 1.0.2 3 Logic Configurations Figure 2 through Figure 8 show the logical functions that can be implemented using the 74AUP1G56. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical implementation is next to the board-level physical implementation of how the pins should be connected. B Y C B Y C 1 2 3 6 5 4 B Y C VCC B Y C B Y C 1 2 3 6 5 4 B Y C VCC Figure 2. 2-Input AND Gate or 2-Input NOR with Both Inputs Inverted Figure 3. 2-Input NAND with Inverted B Input or 2-Input OR Gate with Inverted C Input A Y C A Y C 1 2 3 6 5 4 A Y C VCC A A Y C A Y C 1 2 3 6 5 4 Y C VCC Figure 4. 2-Input NAND with Inverted C Input or 2-Input OR Gate with Inverted A Input Figure 5. 2-Input NOR Gate or 2-Input AND Gate with Both Inputs Inverted B Y C 1 2 3 6 5 4 Y C VCC B 1 2 3 3 6 5 4 Y VCC Y A A Figure 6. 2-Input XNOR Gate Figure 7. Inverter 1 2 3 6 5 4 Y VCC Y B B Figure 8. Non-Inverter Buffer |
Аналогичный номер детали - 74AUP1G56 |
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Аналогичное описание - 74AUP1G56 |
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