Sample Rate: 3 MSPS and AIN = –0.5 dB

1

3

4

5

78

9

6

2

THD = –74.42dB

S/(N+D) = 68.83dB

SFDR = –78.79dB

HARMONICS – dB

2ND

–79

6TH

–86

3RD

–86

7TH

–93

4TH

–78

8TH

–95

5TH

–81

9TH

–96

AD1672–Dynamic Characteristics

REV. 0

–8–

1

3

4

5

7

8

9

6

THD = –60.12dB

S/(N+D) =59.70dB

SFDR = –61.09dB

HARMONICS – dB

2ND

–61

6TH

–79

3RD

–67

7TH

–91

4TH

–98

8TH

–93

5TH

–78

9TH

–87

2

THEORY OF OPERATION

The AD1672 is implemented using a 4-stage pipelined multiple

flash architecture. The flash resolution for the stages is 4-4-3-4

with one-bit of overlap used between stages for error correction.

A low noise sample-and-hold amplifier (SHA) acquires a full-

scale, single-ended input to 12-bit accuracy within 167 ns. A

4-bit approximation of the input is made by the first flash con-

verter, and an accurate analog representation of this four-bit es-

timate is generated by a digital-to-analog (DAC) converter.

This approximation is subtracted from the SHA output to pro-

duce a remainder, or residue. This residue is then sampled and

held by the second SHA, and a 4-bit approximation is generated

and subtracted by the second stage. Once the second SHA goes

into hold, the first stage goes back into sample mode to acquire a

new input signal.

The third stage which has 3 bits of resolution is similar to the

first and second stage in that each stage consists of a SHA, flash

ADC, and a DAC. Each stage preforms a 4- (or 3-) bit ap-

proximation/subtraction operation with the residue of each stage

being passed on to the next stage. The fourth or last stage con-

sists only of a 4-bit flash ADC which converts the final residue.

The 15 output bits from the 4 flash converters are accumulated

in the correction logic block, which adds the bits together using

the appropriate correction algorithm, to produce the 12 bit

output word. The digital output, together with the overrange

indicator (OTR), is latched into an output buffer to drive the

output pins.

The additional SHA inserted in each stage of the AD1672 archi-

tecture allows pipelining of the conversion. In essence, the con-

verter is converting multiple inputs simultaneously, processing

them through the converter chain serially. This means that

while the converter is capable of capturing a new input sample

every clock cycle, it actually takes 2 1/2 clock cycles for the con-

version to be fully processed and appear at the output. This

“pipeline delay” is often referred to as latency, and is not a con-

cern in most applications, however there are some cases where it

may be a consideration. For example, some applications call for

the A/D converter to be placed in a high speed feedback loop,

where its input is servoed to provide a desired result at the digi-

tal output (e.g., offset calibration or zero restoration in video

applications). In these cases the clock cycle delay through the

pipeline must be accounted for in the loop stability calculations.

Also, because the converter is working on three conversions si-

multaneously major disruptions to the part (such as a large

glitch on the supplies or reference) may corrupt three data

samples. Finally, there will be a minimum clock rate below

which the SHA droop corrupts the signal in the pipeline. In the

case of the AD1672, this minimum clock rate is 20 kHz at

25

°C.

The AD1672 clock circuitry uses both edges of the clock in its

internal timing circuitry (see specification page for exact timing

requirements). The AD1672 samples the analog input on the

rising edge of the clock input. During the clock low time (be-

tween the falling edge and rising edge of the clock), the input

SHA is in sample mode; during the clock high time it is in hold.

System disturbances just prior to the rising edge of the clock

may cause the part to acquire the wrong value, and should be

minimized. While the part uses both clock edges for its timing,

jitter is only a significant issue for the rising edge of the clock

(see CLOCK INPUT section).