AD1852

–10–

REV. 0

Control Register

Table V shows the functions of the control register. The control

register is addressed by having an ‘01’ in the bottom two bits of

the 16-bit SPI word. The top 14 bits are then used for the con-

trol register.

De-Emphasis

The AD1852 has a built-in de-emphasis filter that can be used

to decode CDs that have been encoded with the standard

“redbook” 50

µs/15 µs emphasis response curve. Three curves

are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam-

pling rates. The external “DEEMP” pin (Pin 9) turns on the

44.1 kHz de-emphasis filter. The other filters may be selected by

writing to Control Bits 2 and 3 in the control register. If the SPI

port is used to control the de-emphasis filter, the external DEEMP

pin should be tied LO.

Output Impedance

The output impedance of the AD1852 is 65

Ω ± 30%.

Reset

The AD1852 may be reset either by a dedicated hardware pin

(

RESET, Pin 24) or by software, via the SPI control port. While

reset is active, normal operation of the AD1852 is suspended and

Table V.

Bit 11

Bit 10

Bit 9:8

Bit 7

Bit 6

Bit 5:4

Bit 3:2

INT2

× Mode

INT4

× Mode

Number of

Reset.

Soft Mute OR’d Serial Mode OR’d

De-Emphasis Filter

OR’d with Pin 7

OR’d with Pin 10

Bits in Right-

Default = 0

with Pin.

with Mode Pins.

Select.

(192/

48).

(96/

48).

Justified Serial

Default = 0

IDPM1:IDPM0

0:0 No Filter

Default = 0

Default = 0

Mode.

0:0 Right-Justified

0:1 44.1 kHz Filter

0:0 = 24

1:0 32 kHz Filter

0:1 = 20

1:0 Left-Justified

1:1 48 kHz Filter

1:0 = 16

1:1 DSP Mode

Default = 0:0

Default = 0:0

Default = 0:0

the outputs assume midscale values. The AD1852 should always

be reset at power up. The

RESET function should be active for

a minimum of 64 master clock periods. When the

RESET func-

tion becomes inactive, normal operation will continue after a

delay equal to the group delay plus three MCLK periods.

Using the

RESET pin, the internal registers will be set to their

default values, when the

RESET pin is active low. Default

operation will then be enabled when the

RESET pin is raised.

Alternatively, the internal registers can be reset to their default

values by setting Bit 7, of the internal control register, high.

When Bit 7 is reset low, default operation will continue. The

software reset differs from the hardware reset because the soft

reset does not affect the values stored in the SPI registers.

Control Signals

The IDPM0 and IDPM1 control inputs are normally connected

HI or LO to establish the operating state of the AD1852. They

can be changed dynamically (and asynchronously to L/

RCLK

and the master clock), but it is possible that a click or pop sound

may result during the transition from one serial mode to another.

If possible, the AD1852 should be placed in mute before such a

change is made.