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AD671SD-750 датащи(PDF) 9 Page - Analog Devices |
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AD671SD-750 датащи(HTML) 9 Page - Analog Devices |
9 / 16 page AD671 REV. B –9– AIN REF IN BPO/UPO ACOM BIT1 BIT12 DCOM AD671 ENCODE DAV OTR MSB 20 23 24 17 22 18 19 21 13 14 15 16 V CC V EE V LOGIC 5V ± 6 4 8 15V + 2 1 µF +V IN V OUT NOISE REDUCTION GND 1 12 AD586 U3 C14 6.8 µF C15 U4 Figure 5. AD586 as Reference Input for AD671 GROUNDING AND DECOUPLING RULES Proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. The AD671 separates analog and digital grounds to optimize the manage- ment of analog and digital ground currents in a system. The AD671 is designed to minimize the current flowing from ACOM (Pin 22) by directing the majority of the current from VCC (+5 V–Pin 23) to VEE (–5 V–Pin 24). Minimizing analog ground currents hence reduces the potential for large ground voltage drops. This can be especially true in systems that do not utilize ground planes or wide ground runs. ACOM is also con- figured to be code independent, therefore reducing input depen- dent analog ground voltage drops and errors. The input current supplied by the external reference (REFIN–Pin 19) and the ma- jority of the full-scale input signal (AIN–Pin 20) are also di- rected to VÉE. Also critical in any high speed digital design are the use of proper digital grounding techniques to avoid potential CMOS “ground bounce.” Figure 6 is provided to assist in the proper layout, grounding and decoupling techniques. Table I is a list of grounding and decoupling guidelines that should be reviewed before laying out a printed circuit board. AIN REF IN BPO/UPO ACOM BIT1 BIT12 DCOM AD671 ENCODE DAV OTR MSB 20 23 24 17 22 18 19 21 13 14 15 16 V CC V EE V LOGIC 5V ± 1 12 V IN + – +5V REF *GROUND PLANE RECOMMENDED 0.1 µF 10 µF 10 µF10µF 0.1 µF 0.1 µF +5V +5V –5V AGP* DGP* Figure 6. AD671 Grounding and Decoupling Table I. Grounding and Decoupling Guidelines Power Supply Decoupling Comment Capacitor Values 0.1 µF (Ceramic) and 10 µF (Tantalum). (Surface Mount Chip Capacitors Recom- mended to Reduce Lead Inductance). Capacitor Locations Directly at Positive and Negative Supply Pins to Respective Ground Plane. Grounding Analog Ground Ground Plane or Wide Ground Return Connected to the Analog Power Supply. Digital Ground Ground Plane or Wide Ground Return Connected to the Digital Power Supply. Analog and Digital Ground Connected Together Once at the AD671. UNIPOLAR (0 V TO +10 V) CALIBRATION The AD671 is factory trimmed to minimize offset, gain and lin- earity errors. In some applications the offset and gain errors of the AD671 need to be externally adjusted to zero. This is ac- complished by trimming the voltage at BPO/UPO (Pin 21) and REFIN (Pin 19). In those applications the AD588, a high preci- sion pin programmable voltage reference, is an ideal choice. The AD588 includes a reference cell and three additional amplifiers which can be configured to provide offset and gain trims for the AD671. The circuit in Figure 7 is recommended for calibrating offset and gain errors of the AD671 when configured in the 0 V to +10 V input range. AIN REF IN BPO/UPO ACOM BIT1 BIT12 DCOM AD671 ENCODE DAV OTR MSB 20 23 24 17 22 18 19 21 13 14 15 16 V CC V EE V LOGIC 1 12 0.1 µF 10 µF 10 µF10µF 0.1 µF 0.1 µF +5V +5V –5V 0 TO 10V + 10 µF 0.1 µF 10 µF 1 14 15 50 1 µF 150 13 12 11 8 10 9 5 7 6 4 3 5k R2 100k 50 1 µF AD588 0.1 µF 150pF 10k 39k 15V + 2 16 +15 –15 R1 100 Figure 7. Unipolar (0 V to +10 V) Calibration The AD671 is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above it and below it). Thus, the first transition ( from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (1.22 mV for 10 V range). If the offset trim resistor R2 is used, |
Аналогичный номер детали - AD671SD-750 |
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Аналогичное описание - AD671SD-750 |
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