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AD7302BRU датащи(PDF) 9 Page - Analog Devices |
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AD7302BRU датащи(HTML) 9 Page - Analog Devices |
9 / 16 page AD7302 –9– REV. 0 GENERAL DESCRIPTION D/A Section The AD7302 is a dual 8-bit voltage output digital-to-analog converter. The architecture consists of a reference amplifier, a current source DAC followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the DAC. Figure 19 shows a block diagram of the basic DAC architecture. REFERENCE AMPLIFIER + - VO A/B VDD REFIN AD7302 CURRENT DAC I/V 30k Ω 30k Ω 11.7k Ω 11.7k Ω Figure 19. DAC Architecture Both DAC A and DAC B outputs are internally buffered and these output buffer amplifiers have rail-to-rail output character- istics. The output amplifier is capable driving a load of 10 k Ω to both VDD and ground in parallel with a 100 pF to ground. The reference selection for the DAC can either be internally generated from VDD or externally applied through the REFIN pin. A comparator on the REFIN pin detects whether the required reference is the internally generated reference or the externally applied voltage to the REFIN pin. If REFIN is connected to VDD, the reference selected is the internally generated VDD/2 reference. When an externally applied voltage is more than one volt below VDD, the comparator selection switches to the externally applied voltage to the REFIN pin. The range on the external reference input is from 1.0 V to VDD/2. The output voltage from either DAC is given by: VO A/B = 2 × V REF × (N/256) where: VREF is the voltage applied to the external REFIN pin or VDD/2 when the internal reference is selected. N is the decimal equivalent of the code loaded to the DAC register and ranges from 0 to 255. Reference The AD7302 has the facility to use either an external reference applied through the REFIN pin or an internal reference generated from VDD. Figure 20 shows the reference input arrangement where either the internal VDD/2 reference or the externally applied reference can be selected. COMPARATOR VTH PMOS MUX INT REF SELECTED REFERENCE OUTPUT VDD REFIN INT REF EXT REF Figure 20. Reference Selection Circuitry The internal reference is selected by tying the REFIN pin to VDD. If an external reference is to be used, this can be directly applied to the REFIN pin; if this is 1 V below VDD, the internal circuitry will select this externally applied reference as the reference source for the DAC. Digital Interface The AD7302 contains a fast parallel interface allowing this dual DAC to interface to industry standard microprocessors, micro- controllers and DSP machines. There are two modes in which this parallel interface can be configured to update the DAC outputs. The simultaneous update mode allows simultaneous updating of both DAC outputs. The automatic update mode allows each DAC to be individually updated following a write cycle. Figure 21 shows the internal logic associated with the digital interface. The PON STRB signal is internally generated from the power on reset circuitry and is low during the power- on reset phase of the power-up procedure. CLR PON STRB LDAC A/B CS WR CLEAR LDAC DAC A SEL DAC A CONTROL LOGIC ENABLE SET SLE MLE A SLE A CLR CLEAR LDAC DAC B SEL DAC B CONTROL LOGIC ENABLE SET SLE MLE B SLE B Figure 21. Logic Interface The AD7302 has a double buffered interface, which allows for simultaneous updating of the DAC outputs. Figure 22 shows a block diagram of the register arrangement within the AD7302. DB7–DB0 INPUT REGISTER LOWER NIBBLE 4 TO 15 DECODER DAC REGISTER DRIVERS 4 15 15 30 8 UPPER NIBBLE 4 TO 15 DECODER DAC REGISTER DRIVERS 4 15 15 30 CONTROL LOGIC SLE MLE A/B CS WR LDAC CLR Figure 22. Register Arrangement |
Аналогичный номер детали - AD7302BRU |
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Аналогичное описание - AD7302BRU |
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