AD7723

–10–

REV. 0

PARALLEL MODE PIN FUNCTION DESCRIPTIONS

Mnemonic

Pin No.

Description

30

Chip Select Logic Input.

CFMT/

RD

4

Read Logic Input. Used in conjunction with

CS to read data from the parallel bus. The output data

bus is enabled when the rising edge of CLKIN senses a logic low level on

RD if CS is also low. When

RD is sensed high, the output data bits, DB15–DB0 will be high impedance.

DGND/

DRDY

5

Data Ready Logic Output. A falling edge indicates a new output word is available to be read from

the output data register.

DRDY will return high upon completion of a read operation. If a read operation

does not occur between output updates,

DRDY will pulse high for two CLKIN cycles before the next

output update.

DRDY also indicates when conversion results are available after a SYNC sequence.

DGND/DB15

31

Data Output Bit, (MSB)

DGND/DB14

32

Data Output Bit.

SCR/DB13

33

Data Output Bit.

SLDR/DB12

34

Data Output Bit.

SLP/DB11

35

Data Output Bit.

TSI/DB10

36

Data Output Bit.

FSO/DB9

37

Data Output Bit.

SDO/DB8

38

Data Output Bit.

SCO/DB7

40

Data Output Bit.

FSI/DB6

41

Data Output Bit.

SFMT/DB5

42

Data Output Bit.

DOE/DB4

43

Data Output Bit.

DGND/DB3

44

Data Output Bit.

DGND/DB2

1

Data Output Bit.

DGND/DB1

2

Data Output Bit.

DGND/DB0

3

Data Output Bit, (LSB).