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AD7817ARU-REEL7 датащи(PDF) 5 Page - Analog Devices |
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AD7817ARU-REEL7 датащи(HTML) 5 Page - Analog Devices |
5 / 20 page REV. C AD7816/AD7817/AD7818 –5– TIMING CHARACTERISTICS1, 2 Parameter A, B Versions Unit Test Conditions/Comments tPOWER-UP 2 µs max Power-Up Time from Rising Edge of CONVST t1a 9 µs max Conversion Time Channels 1 to 4 t1b 27 µs max Conversion Time Temperature Sensor t2 20 ns min CONVST Pulse Width t3 50 ns max CONVST Falling Edge to BUSY Rising Edge t4 0 ns min CS Falling Edge to RD/WR Falling Edge Setup Time t5 0 ns min RD/ WR Falling Edge to SCLK Falling Edge Setup t6 10 ns min DIN Setup Time before SCLK Rising Edge t7 10 ns min DIN Hold Time after SCLK Rising Edge t8 40 ns min SCLK Low Pulse Width t9 40 ns min SCLK High Pulse Width t10 0 ns min CS Falling Edge to RD/WR Rising Edge Setup Time t11 0 ns min RD/ WR Rising Edge to SCLK Falling Edge Setup Time t12 3 20 ns max DOUT Access Time after RD/WR Rising Edge t13 3 20 ns max DOUT Access Time after SCLK Falling Edge t14a 3, 4 30 ns max DOUT Bus Relinquish Time after Falling Edge of RD/WR t14b 3, 4 30 ns max DOUT Bus Relinquish Time after Rising Edge of CS t15 150 ns max BUSY Falling Edge to OTI Falling Edge t16 40 ns min RD/ WR Rising Edge to OTI Rising Edge t17 400 ns min SCLK Rising Edge to CONVST Falling Edge (Acquisition Time of T/H) NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 16, 17, 20 and 21. 3These figures are measured with the load circuit of Figure 3. They are defined as the time required for D OUT to cross 0.8 V or 2.4 V for VDD = 5 V 10% and 0.4 V or 2 V for VDD = 3 V 10%, as quoted on the specifications page of this data sheet. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice. 1.6V IOL 200 A 200 A IOL TO OUTPUT PIN CL 50pF Figure 3. Load Circuit for Access Time and Bus Relinquish Time (VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX unless otherwise noted) |
Аналогичный номер детали - AD7817ARU-REEL7 |
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Аналогичное описание - AD7817ARU-REEL7 |
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