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AD7868BN датащи(PDF) 7 Page - Analog Devices |
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AD7868BN датащи(HTML) 7 Page - Analog Devices |
7 / 16 page AD7868 –7– REV. B 500 200 100 50 20 10 50 100 200 1k 2k 10k 20k 100k FREQUENCY – Hz REF OUT DAC OUTPUT WITH ALL 0s LOADED REF OUT DECOUPLED AS SHOWN IN FIGURE 2 TA = +25°C VDD = +5V VSS = –5V Figure 3. Noise Spectral Density vs. Frequency INPUT/OUTPUT TRANSFER FUNCTIONS A bipolar circuit for the AD7868 is shown in Figure 4. The ana- log input/output voltage range of the AD7868 is ±3 V. The de- signed code transitions for the ADC occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB . . . FS – 3/2 LSBs). The input/output code is 2s complement binary with 1 LSB = FS/4096 = 1.46 mV. The ideal transfer function is shown in Figure 5. AD7868* RO ADC RI DAC AGND *ADDITIONAL PINS OMITTED FOR CLARITY VIN VOUT ANALOG OUTPUT RANGE = ±3V ANALOG INPUT RANGE = ±3V R1 200 C2 0.1µF C1 10µF Figure 4. AD7868 Basic Bipolar Operation Using RO ADC as a Reference Input for the DAC -FS 2 FS = 6V 1LSB = FS 4096 0V 011...111 011...110 000...010 000...001 000...000 111...111 111...110 100...001 100...000 INPUT VOLTAGE OUTPUT CODE 2 -1LSB FS + Figure 5. AD7868 Input/Output Transfer Function OFFSET AND FULL-SCALE ADJUSTMENT In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale errors do not cause problems as long as the input signal is within the full dynamic range of the ADC. For applications which require that the input signal range match the full analog input dynamic range of the ADC, offset and full-scale errors have to be adjusted to zero. ADC ADJUSTMENT Figure 6 has signal conditioning at the input and output of the AD7868 for trimming the end points of the transfer functions of both the ADC and the DAC. Offset error must be adjusted be- fore full-scale error. For the ADC, this is achieved by trimming the offset of A1 while the input voltage, V1, is 1/2 LSB below ground. The trim procedure is as follows: apply a voltage of –0.73 mV (–1/2 LSB) at V1 in Figure 6 and adjust the offset voltage of A1 until the ADC output code flickers between 1111 1111 1111 (FFF HEX) and 0000 0000 0000 (000 HEX). ADC gain error can be adjusted at either the first code transi- tion (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows (see Figure 6). ADC Positive Full-Scale Adjustment Apply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2 until the ADC output code flickers between 0111 1111 1110 (7FE HEX) and 0111 1111 1111 (7FF HEX). ADC Negative Full-Scale Adjustment Apply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 (800 HEX) and 1000 0000 0001 (801 HEX). DAC ADJUSTMENT Op amp A2 is included in Figure 6 for the DAC transfer func- tion adjustment. Again offset must be adjusted before full scale. To adjust offset: load the DAC with 0000 0000 0000 (000 HEX) and trim the offset of A2 to 0 V. As with the ADC adjust- ment, gain error can be adjusted at either the first code transi- tion (DAC negative full scale) or the last code transition (DAC positive full scale). The trim procedures for both cases are as follows: DAC Positive Full-Scale Adjustment Load the DAC with 0111 1111 1111 (7FF HEX) and adjust R7 until the op amp output voltage is equal to 2.9985 V, (FS/2 – 1 LSB). DAC Negative Full-Scale Adjustment Load the DAC with 1000 0000 0000 (800 HEX) and adjust R7 until the op amp output voltage is equal to 3.0 V (–FS/2). AD7868* *ADDITIONAL PINS OMITTED FOR CLARITY AGND A1 V1 INPUT VOLTAGE RANGE = ±3V R1 10k R2 500 R3 10k R5 10k R4 10k VIN VOUT A2 R6 10k R7 500 R8 10k R10 10k R9 10k V0 OUTPUT VOLTAGE RANGE = ± 3V Figure 6. AD7868 with Input/Output Adjustment |
Аналогичный номер детали - AD7868BN |
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Аналогичное описание - AD7868BN |
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