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AD9101SE датащи(PDF) 6 Page - Analog Devices |
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AD9101SE датащи(HTML) 6 Page - Analog Devices |
6 / 12 page AD9101 –6– REV. 0 should be removed from around the VIN and VOUT pins to mini- mize coupling onto the analog signal path. While a single ground plane is recommended, the analog signal and differential ECL clock ground currents follow a narrow path directly under their common voltage signal line. To reduce re- flections, especially when terminations are used for transmission line efficiency, the clock, VIN, and VOUT signals and respective ground paths should not cross each other; if they do, unwanted coupling can result. Analog terminations should be kept as far as possible from the power supply decoupling capacitors to mini- mize supply current spike feedthrough. Driving the Encode Clock The AD9101 requires a differential ECL clock command. Due to the high gain bandwidth of the AD9101 internal switch, the input clock should have a slew rate of at least 400 V/ µs. To obtain maximum signal to noise performance, especially at high analog input frequencies, a low jitter clock source is re- quired. The AD9101 clock can be driven by an AD96685, an ultrahigh speed ECL comparator with very low jitter. Figure 2 illustrates a recommended termination for the differen- tial encode clock inputs of the AD9101. The 40 Ω R LS is re- quired to level shift the ECL voltages more negative. This increases the linear signal range of the sampler. When the input is less than 600 mV (2.4 V p-p output), these level shift resistors are not required. 40 510 –5.2 V –5.2 V 40 510 CLK CLK 10 RLS 11 RLS Figure 2. Recommended Encode Clock Termination When driving the encode clock from a remote circuit via transmission lines, or where stray capacitance exceeds 2 pF, Thevenin equivalent terminations should be used (270 Ω to –5.2 V and 160 Ω to ground). For this 100 Ω equivalent termi- nation, RLS should be 20 Ω. Driving the Analog Input Special care must be taken to ensure that the analog input signal is not compromised before it reaches the AD9101. To obtain maximum signal to noise performance, a very low phase noise analog source is required. In addition, input filtering and/or a low harmonic signal source is necessary to maximize the spuri- ous free dynamic range. Any required filtering should be located close to the AD9101 and away from digital lines. Matching the AD9101 to A/D Encoders The AD9101’s analog output level may have to be offset or am- plified to match the full-scale range of a given A/D converter. This can generally be accomplished by inserting an amplifier af- ter the AD9101. For example, the AD671 is a 12-bit 500 ns monolithic ADC encoder that requires a 0 V to +5 V full-scale analog input. An AD84X series amplifier could be used to con- dition the AD9101 output to match the full-scale range of the AD671. The AD9101 can perform a dc level shift function when its input is bipolar and the ADC requires a unipolar signal. The AD9002 The architecture of the AD9101 minimizes hold mode distor- tion over its specified frequency range. As an example, in track mode the worst harmonic generated for a 20 MHz input tone is typically –65 dBFS. In hold mode, under the same conditions and sampling at 50 MSPS, the worst harmonic generated is –75 dBFS. The reason is the output amplifier in hold mode has only a dc distortion relevancy. With its inherent linearity (7 ns settling to 0.01%), the output amplifier has essentially settled to its dc distortion level even for track plus hold times as short as 20 ns. For a traditional open-loop output buffer, the ac (track mode) and dc (hold mode) distortion levels are often the same. Droop Rate Droop rate does not necessarily affect a track-and-hold’s distor- tion characteristics. If the droop rate is constant versus the input voltage for a given hold time, it manifests itself as a dc offset to the encoder. For the AD9101, the droop rate is typically 3 mV/ µs. If a signal is held for 1 µs, a subsequent encoder will see a 3 mV offset voltage. If there is no droop sensitivity to the held voltage value, the offset would be constant and “ride” on the input signal and introduce no hold-mode nonlinearities. When droop rate varies proportionately to the level of the held voltage signal level, only a gain error is introduced to the A/D encoder. The AD9101 has a droop sensitivity to the input level of 20 mV/V µs. For a 2 V p-p output signal, this translates to a 1%/ µs gain error and does not cause additional distortion errors. However, hold times longer than about 500 ns can cause distor- tion due to the R × HC time constant at the hold capacitor. In addition, hold mode noise will increase linearly vs. hold time and thus degrade SNR performance. Layout Considerations For best performance results, good high speed design tech- niques must be applied. The component (top) side ground plane should be as large as possible; two-ounce copper cladding is preferable. All runs should be as short as possible, and de- coupling capacitors must be used. The schematic of a recommended AD9101 evaluation board is shown. (Contact factory concerning availability of assembled boards.) All 0.01 µF decoupling capacitors should be low induc- tance surface mount devices (P/N 05085C103MT050 from AVX) and connected with short lead lengths to minimize stray inductance. The 10 µF, low frequency tantalum power supply decoupling capacitors should be located within 1.5 inches of the AD9101. The common 0.01 µF supply capacitors can be wired together. The common power supply bus (connected to the 10 µF capaci- tor and power supply source) can be routed to the underside of the board to the daisy chain wired 0.01 µF supply capacitors. For remote input and/or output drive applications, controlled impedances are required to minimize line reflections which will reduce signal fidelity. When capacitive and/or high impedance levels are present, the load and/or source should be physically located within approximately one inch of the AD9101. Note that a series resistance, RS, is required if the load is greater than 6 pF. (The Recommended RS vs. CL chart in the “Typical Per- formance Section” shows values of RS for various capacitive loads which result in no more than a 20% increase in settling time for loads up to 80 pF.) For best results when driving heavily capacitive or low resistance loads, the AD9630 buffer is strongly suggested. As much of the ground plane as possible |
Аналогичный номер детали - AD9101SE |
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Аналогичное описание - AD9101SE |
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