ADF4001BCP datasheet(1/16 Pages) AD

номер детали	ADF4001BCP

подробное описание детали	200 MHz Clock Generator PLL

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a

ADF4001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

200 MHz Clock Generator PLL

FUNCTIONAL BLOCK DIAGRAM

RFINA

RFINB

13-BIT

N COUNTER

LOCK DETECT

CURRENT

SETTING 1

CPI3

CPI2

CPI1 CPI6 CPI5

CPI4

M1

M3

M2

SDOUT

AVDD

REFIN

CLK

DATA

LE

AVDD

DVDD

VP

CPGND

RSET

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

24-BIT

INPUT REGISTER

N COUNTER

LATCH

SDOUT

22

14

ADF4001

MUXOUT

MUX

HIGH Z

CURRENT

SETTING 2

CHARGE

PUMP

CP

CE

AGND

DGND

PHASE

FREQUENCY

DETECTOR

REFERENCE

13

FEATURES

200 MHz Bandwidth

2.7 V to 5.5 V Power Supply

Separate Charge Pump Supply (VP) Allows Extended

Tuning Voltage in 5 V Systems

Programmable Charge Pump Currents

3-Wire Serial Interface

Hardware and Software Power-Down Mode

Analog and Digital Lock Detect

Hardware-Compatible to the ADF4110/ADF4111/

ADF4112/ADF4113

Typical Operating Current 4.5 mA

Ultralow Phase Noise

16-Lead TSSOP

20-Lead Chip Scale Package

APPLICATIONS

Clock Generation

Low Frequency PLLs

Low Jitter Clock Source

Clock Smoothing

Frequency Translation

SONET, ATM, ADM, DSLAM, SDM

GENERAL DESCRIPTION

The ADF4001 clock generator can be used to implement clock

sources for PLLs that require very low noise, stable refer-

ence signals. It consists of a low-noise digital PFD (Phase

Frequency Detector), a precision charge pump, a programmable

reference divider, and a programmable 13-bit N counter. In

addition, the 14-bit reference counter (R Counter) allows

selectable REFIN frequencies at the PFD input. A complete

PLL (Phase-Locked Loop) can be implemented if the synthesizer

is used with an external loop filter and VCO (Voltage Controlled

Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).

The N min value of 1 allows flexibility in clock generation.

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