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ADF4112 датащи(PDF) 1 Page - Analog Devices |
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ADF4112 датащи(HTML) 1 Page - Analog Devices |
1 / 24 page REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADF4110/ADF4111/ADF4112/ADF4113 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 RF PLL Frequency Synthesizers FEATURES ADF4110: 550 MHz ADF4111: 1.2 GHz ADF4112: 3.0 GHz ADF4113: 4.0 GHz 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Antibacklash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode APPLICATIONS Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment GENERAL DESCRIPTION The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and down- conversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be imple- mented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM REFERENCE N = BP + A FUNCTION LATCH PRESCALER P/P +1 13-BIT B COUNTER 6-BIT A COUNTER 14-BIT R COUNTER 24-BIT INPUT REGISTER R COUNTER LATCH A, B COUNTER LATCH PHASE FREQUENCY DETECTOR CHARGE PUMP M3 M2 M1 HIGH Z MUX MUXOUT CP AVDD SDOUT 19 13 14 22 SDOUT FROM FUNCTION LATCH DGND AGND CE RFINB RFINA LE DATA CLK REFIN CPGND VP DVDD AVDD LOCK DETECT ADF4110/ADF4111 ADF4112/ADF4113 RSET CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 1 6 LOAD LOAD |
Аналогичный номер детали - ADF4112 |
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Аналогичное описание - ADF4112 |
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