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ADM1021A датащи(PDF) 2 Page - Analog Devices |
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ADM1021A датащи(HTML) 2 Page - Analog Devices |
2 / 16 page –2– REV. D ADM1021A–SPECIFICATIONS (T A = TMIN to TMAX 1, V DD = 3.0 V to 3.6 V, unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY AND ADC Temperature Resolution 1 °C Guaranteed No Missed Codes Temperature Error, Local Sensor ±1 °C –3 +3 °C Temperature Error, Remote Sensor –3 +3 °CT A = 60 °C to 100°C –5 +5 °C Supply Voltage Range 3 3.6 V Note 2 Undervoltage Lockout Threshold 2.5 2.7 2.95 V VDD Input, Disables ADC, Rising Edge Undervoltage Lockout Hysteresis 25 mV Power-On Reset Threshold 0.9 1.7 2.2 V VDD, Falling Edge 3 POR Threshold Hysteresis 50 mV Standby Supply Current 1 5 µAV DD = 3.3 V, No SMBus Activity 4 µA SCLK at 10 kHz Average Operating Supply Current 130 200 µA 0.25 Conversions/Sec Rate Autoconvert Mode, Averaged Over 4 Seconds 225 330 µA2 Conversions/Sec Rate Conversion Time 65 115 170 ms From Stop Bit to Conversion Complete (Both Channels) D+ Forced to D– + 0.65 V Remote Sensor Source Current 120 205 300 µAHigh Level3 712 16 µALow Level3 D-Source Voltage 0.7 V Address Pin Bias Current (ADD0, ADD1) 50 µAMomentary at Power-On Reset SMBUS INTERFACE Logic Input High Voltage, VIH 2.2 V VDD = 3 V to 5.5 V STBY, SCLK, SDATA Logic Input Low Voltage, VIL 0.8 V VDD = 3 V to 5.5 V STBY, SCLK, SDATA SMBus Output Low Sink Current 6 mA SDATA Forced to 0.6 V ALERT Output Low Sink Current 1 mA ALERT Forced to 0.4 V Logic Input Current, IIH, IIL –1 +1 µA SMBus Input Capacitance, SCLK, SDATA 5 pF SMBus Clock Frequency 100 kHz SMBus Clock Low Time, tLOW 4.7 µst LOW between 10% Points SMBus Clock High Time, tHIGH 4 µstHIGH between 90% Points SMBus Start Condition Setup Time, tSU:STA 4.7 µs SMBus Repeat Start Condition 250 ns Between 90% and 90% Points Setup Time, tSU:STA SMBus Start Condition Hold Time, tHD:STA 4 µsTime from 10% of SDATA to 90% of SCLK SMBus Stop Condition Setup Time, tSU:STO 4 µsTime from 90% of SCLK to 10% of SDATA SMBus Data Valid to SCLK 250 ns Time from 10% or 90% of SDATA to 10% Rising Edge Time, tSU:DAT of SCLK SMBus Data Hold Time, tHD:DAT 0 µs SMBus Bus Free Time, tBUF 4.7 µsBetween Start/Stop Conditions SCLK Falling Edge to SDATA 1 µsMaster Clocking in Data Valid Time, tVD, DAT NOTES 1T MAX = 100 °C; T MIN = 0 °C. 2Operation at V DD = 5 V guaranteed by design, not production tested. 3Guaranteed by design, not production tested. Specifications subject to change without notice. |
Аналогичный номер детали - ADM1021A |
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Аналогичное описание - ADM1021A |
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