ADV7123

–9–

REV. B

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

1–10

G0–G9

R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to

either the regular PCB power or ground plane.

11

BLANK

Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the analog

outputs, IOR, IOB, and IOG, to the blanking level. The

BLANK signal is latched on the rising edge

of CLOCK. While

BLANK is a logical zero, the R0–R9, G0–G9, and B0–B9 pixel inputs are ignored.

12

SYNC

Composite Sync Control Input (TTL Compatible). A logical zero on the

SYNC input switches off a

40 IRE current source. This is internally connected to the IOG analog output.

SYNC does not over-

ride any other control or data input; therefore, it should only be asserted during the blanking interval.

SYNC is latched on the rising edge of CLOCK.

If sync information is not required on the green channel, the

SYNC input should be tied to logical zero.

Analog Power Supply (5 V

14–23

B0–B9

R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to

either the regular PCB power or ground plane.

24

CLOCK

Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,

SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system.

CLOCK should be driven by a dedicated TTL buffer.

25, 26

GND

Ground. All GND pins must be connected.

27, 31, 33

IOB, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB

video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated

75

Ω load. If the complementary outputs are not required, these outputs should be tied to ground.

28, 32, 34 IOB, IOG, IOR

Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly

driving a doubly terminated 75

Ω coaxial cable. All three current outputs should have similar output

loads whether or not they are all being used.

35

COMP

Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1

µF ceramic

36

Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)

37

signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. For

nominal video levels into a doubly terminated 75

Ω load, R

Ω.

to IOG) is given by:

IOG (mA)

= 11,445

IOR, IOB (mA)

= 7,989.6

The equation for IOG will be the same as that for IOR and IOB when

SYNC is not being used, i.e.,

SYNC tied permanently low.

38

PSAVE

Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.

39–48

R0–R9

Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of

CLOCK.