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AD8362ARUZ-REEL71 датащи(PDF) 7 Page - Analog Devices |
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AD8362ARUZ-REEL71 датащи(HTML) 7 Page - Analog Devices |
7 / 36 page AD8362 Rev. B | Page 7 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTION TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM VREF VTGT VPOS VOUT VSET ACOM CLPF AD8362 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description Equivalent Circuit 1, 8 COMM Common Connection. Connect via low impedance to system common. 2 CHPF Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter. 3, 6 DECL Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete input circuit. 4 INHI High Signal Input Terminal. Part of a differential input port with INLO. Circuit A 5 INLO Low Signal Input Terminal. Part of a differential input port with INHI. Circuit A 7 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362. 9 CLPF Connection for loop filter integration (averaging) capacitor, the other pin of which is usually grounded via a resistor to improve loop stability and response time. 10, 16 ACOM Analog Common Connection for Output Amplifier. 11 VSET The voltage applied to this pin sets the decibel value of the required RF input voltage that results in zero current out of CLPF and thus the loop integrating capacitor. Circuit B 12 VOUT Output of Error Amplifier. In measurement mode, normally connected directly to VSET. Circuit C 13 VPOS Connect to 5 V Power Supply. 14 VTGT The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity. Circuit D 15 VREF General-Purpose Reference Voltage Output of 1.25 V (usually connected only to VTGT). Circuit E |
Аналогичный номер детали - AD8362ARUZ-REEL71 |
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Аналогичное описание - AD8362ARUZ-REEL71 |
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