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FW801A-DB датащи(PDF) 7 Page - Agere Systems

номер детали FW801A-DB
подробное описание детали  Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device
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производитель  AGERE [Agere Systems]
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FW801A-DB датащи(HTML) 7 Page - Agere Systems

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Data Sheet, Rev. 1
FW801A Low-Power PHY IEEE 1394A-2000
June 2001
One-Cable Transceiver/Arbiter Device
Agere Systems Inc.
7
Signal Information (continued)
Table 1. Signal Descriptions
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Pin
Signal*
Type
Name/Description
17
C/LKON
I/O
Bus Manager Capable Input and Link-On Output. On hardware reset,
this pin is used to set the default value of the contender status indicated
during self-ID. The bit value programming is done by tying the signal
through a 10 k
Ω resistor to VDD (high, bus manager capable) or to GND
(low, not bus manager capable). Using either the pull-up or pull-down
resistor allows the link-on output to override the input value when neces-
sary.
After hardware reset, this pin is set as an output. If the LPS is inactive,
C/LKON indicates one of the following events by asserting a 6.114 MHz
signal.
1. FW801A receives a link-on packet addressed to this node.
2. Port_event register bit is 1.
3. Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the
Resume_int register bit is also 1. Once activated, the C/LKON output will
continue active until the LPS becomes active. The PHY also deasserts
the C/LKON output when a bus reset occurs, if the C/LKON is active due
solely to the reception of a link-on packet.
Note: If an interrupt condition exists which would otherwise cause the C/
LKON output to be activated if the LPS were inactive, the C/LKON
output will be activated when the LPS subsequently becomes inac-
tive.
13
CNA
O
Cable-Not-Active Output. CNA is asserted high when none of the PHY
ports are receiving an incoming bias voltage. This circuit remains active
during the powerdown mode.
20
CPS
I
Cable Power Status. CPS is normally connected to the cable power
through a 400 k
Ω resistor. This circuit drives an internal comparator that
detects the presence of cable power. This information is maintained in
one internal register and is available to the LLC by way of a register read
(see Table 8, Register 0).
1
CTL0
I/O
Control I/O. The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
2CTL1
3, 4, 6, 7,
8, 9, 10,
11
D[0:7]
I/O
Data I/O. The Dn signals are bidirectional and pass data between the
PHY and the LLC. Bus-keeper circuitry is built into these terminals.
19
/ISO
I
Link Interface Isolation Disable Input (Active-Low). /ISO controls the
operation of an internal pulse differentiating function used on the PHY-
LLC interface signals, CTLn and Dn, when they operate as outputs. When
/ISO is asserted low, the isolation barrier is implemented between PHY
and its LLC (as described in Annex J of IEEE 1394-1995). /ISO is nor-
mally tied high to disable isolation differentiation. Bus-keepers are
enabled when
/ISO is high (inactive) on CTL, D, and LREQ. When /
ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note AP98-074CMPR for more information on isolation.


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