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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FW802A датащи(PDF) 4 Page - Agere Systems |
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FW802A датащи(HTML) 4 Page - Agere Systems |
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4 / 24 page  FW802A Low-Power PHY IEEE 1394A-2000 Data Sheet, Rev. 3 Two-Cable Transceiver/Arbiter Device June 2001 4 Agere Systems Inc. Description (continued) resistors that is directly connected to the twisted-pair B (TPB) signals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 k Ω and 220 pF, respectively. The value of the external resistors are specified to meet the standard specifications when connected in parallel with the internal receiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 signals and has a value of 2.49 k Ω ± 1%. The FW802A supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows an FW802A port to be put into a suspended state. In this state, a port is unable to transmit or receive data packets, however, it remains capable of detecting connection status changes and detecting incoming TPBias. When all ports of the FW802A are suspended, all circuits except the bias voltage reference generator, and bias detection circuits are powered down, resulting in significant power savings. The use of suspend/resume is recommended. Four signals are used as inputs to set four configuration status bits in the self-identification (self- ID) packet. These signals are hardwired high or low as a function of the equipment design. PC[0:2] are the three signals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth signal, C/LKON, as an input, indicates whether a node is a contender for bus manager. When the C/LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the self-ID packet, PC0 corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see Table 4-29 of the IEEE 1394-1995 standard for additional details). A powerdown signal (PD) is provided to allow a powerdown mode where most of the PHY circuits are powered down to conserve energy in battery-powered applications. The internal logic in FW802A is reset as long as the powerdown signal is asserted. A cable status signal, CNA, provides a high output when none of the twisted-pair cable ports are receiving incoming bias voltage. This output is not debounced. The CNA output can be used to determine when to power the PHY down or up. In the powerdown mode, all circuitry is disabled except the CNA circuitry. It should be noted that when the device is powered down, it does not act in a repeater mode. When the power supply of the PHY is removed while the twisted-pair cables are connected, the PHY transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the TPBIAS signal voltage on the other end of the cable. For reliable operation, the TPBn signals must be terminated using the normal termination network regardless of whether a cable is connected to a port or not connected to a port. For those applications, when FW802A is used with one of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect- detect circuitry will keep the port in a disconnected state. Note: All gap counts on all nodes of a 1394 bus must be identical. This may be accomplished by using PHY configuration packets (see Section 4.3.4.3 of IEEE 1394-1995 standard) or by using two bus resets, which resets the gap counts to the maximum level (3Fh). The link power status (LPS) signal works with the C/LKON signal to manage the LLC power usage of the node. The LPS signal indicates that the LLC of the node is powered up or powered down. If LPS is inac- tive for more than 1.2 µs and less than 25 µs, PHY/link interface is reset. If LPS is inactive for greater than 25 µs, the PHY will disable the PHY/link interface to save power. FW802A continues its repeater function. If the PHY then receives a link-on packet, the C/LKON signal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the LPS signal communicates this to the PHY and the PHY/link interface is enabled. C/LKON signal is turned off when LPS is active or when a bus reset occurs, provided the interrupt that caused C/LKON is not present. When the PHY/link interface is in the disabled state, the FW802A will automatically enter a low-power mode, if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the FW802A disables its PLL and also disables parts of reference circuitry depending on the state of the ports (some ref- erence circuitry must remain active in order to detect incoming TP bias). The lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports inter- rupt enable bit cleared. The FW802A will exit the low- power mode when the LPS input is asserted high or when a port event occurs that requires the FW802A |
Аналогичный номер детали - FW802A |
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Аналогичное описание - FW802A |
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