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74F113 датащи(PDF) 1 Page - Fairchild Semiconductor |
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74F113 датащи(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 1999 Fairchild Semiconductor Corporation DS009473 www.fairchildsemi.com April 1988 Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip- flop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F113SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F113SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F113PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
Аналогичный номер детали - 74F113 |
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Аналогичное описание - 74F113 |
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