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74F114PC датащи(PDF) 1 Page - Fairchild Semiconductor |
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74F114PC датащи(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 1999 Fairchild Semiconductor Corporation DS009474 www.fairchildsemi.com April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig- gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affect- ing the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of Clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F114SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F114PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
Аналогичный номер детали - 74F114PC |
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Аналогичное описание - 74F114PC |
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