© 2005 Fairchild Semiconductor Corporation

DS012002

www.fairchildsemi.com

February 1994

Revised May 2005

74LCX16373

Low Voltage 16-Bit Transparent Latch

with 5V Tolerant Inputs and Outputs

General Description

The LCX16373 contains sixteen non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch Enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The LCX16373 is designed for low voltage (2.5V or 3.3V)

environment.

The LCX16373 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

s 5V tolerant inputs and outputs

s Power down high impedance inputs and outputs

s Supports live insertion/withdrawal (Note 1)

s

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 500 mA

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

Package Description

74LCX16373G

(Note 2)(Note 3)

BGA54A

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCX16373MEA

(Note 3)

MS48A

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCX16373MTD

(Note 3)

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide