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74LVQ174SC датащи(PDF) 2 Page - Fairchild Semiconductor |
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74LVQ174SC датащи(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page Functional Description The LVQ174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Mas- ter Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output fol- lowing the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW indepen- dent of Clock or Data inputs. The LVQ174 is useful for appli- cations where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs Output MR CP D Q LX X L H N HH H N LL HL X Q H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition Logic Diagram DS011353-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 |
Аналогичный номер детали - 74LVQ174SC |
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Аналогичное описание - 74LVQ174SC |
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