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74LVQ273QSC датащи(PDF) 1 Page - Fairchild Semiconductor |
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74LVQ273QSC датащи(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page 74LVQ273 Low Voltage Octal D-Type Flip-Flop General Description The LVQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D in- put, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The de- vice is useful for applications where the true output only is re- quired and the Clock and Master Reset are common to all storage elements. Features n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75 Ω n 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ273SC M20B 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC 74LVQ273SJ M20D 20-Lead Shrink Molded Small Outline Package, SOIC EIAJ 74LVQ273QSC MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description D 0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q7 Data Outputs DS011358-1 IEEE/IEC DS011358-2 Pin Assignment for SOIC and QSOP DS011358-3 April 1998 © 1998 Fairchild Semiconductor Corporation DS011358 www.fairchildsemi.com |
Аналогичный номер детали - 74LVQ273QSC |
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Аналогичное описание - 74LVQ273QSC |
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