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tures: Figure 6 depicts the relationship between pulse

width variation versus temperatures.

FIGURE 6.

FIGURE 7.

as close to the one-shot device pins as possible to min-

imize stray capacitance, to reduce noise pick-up, and

to reduce I-R and Ldi/dt voltage developed along their

and (7) or pins (14) and (15) is greater than 3 cm, for

example, the output pulse width might be quite different

from values predicted from the appropriate equations.

A non-inductive and low capacitive path is necessary to

operation so that the output pulse width will be accu-

rate.

the internal ground. For optimum system performance

they should be hard wired to the system’s return

ground plane.

frequency standards and practices so that switching

cause interaction between one-shots. A 0.01

µF to 0.10

µF bypass capacitor (disk ceramic or monolithic type)

thermore, the bypass capacitor should be located as

Note: For further detailed device characteristics and output per-

formance please refer to the Fairchild Semiconductor one-shot

application note AN-372.