поискавой системы для электроныых деталей |
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AD9954 датащи(PDF) 6 Page - Analog Devices |
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AD9954 датащи(HTML) 6 Page - Analog Devices |
6 / 40 page AD9954 Rev. B | Page 6 of 40 Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C I 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C I 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C I 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C I 0.8 V Logic 1 Current 25°C V 3 12 μA Logic 0 Current 25°C V 12 μA Input Capacitance 25°C V 2 pF CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V Logic 1 Voltage 25°C I 1.35 V Logic 0 Voltage 25°C I 0.4 V CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V Logic 1 Voltage 25°C I 2.8 V Logic 0 Voltage 25°C I 0.4 V POWER CONSUMPTION (AVDD = DVDD = 1.8 V) Single-Tone Mode (Comparator Off ) 25°C I 162 171 mW With RAM or Linear Sweep Enabled 25°C I 175 190 mW With Comparator Enabled 25°C I 180 190 mW With RAM and Comparator Enabled 25°C I 198 220 mW Rapid Power-Down Mode 25°C I 150 160 mW Full-Sleep Mode 25°C I 20 27 mW SYNCHRONIZATION FUNCTION4 Maximum Sync Clock Rate (DVDD_I/O = 1.8 V) 25°C VI 62.5 MHz Maximum Sync Clock Rate (DVDD_I/O = 3.3 V) 25°C VI 100 MHz SYNC_CLK Alignment Resolution5 25°C V ±1 SYSCLK cycles 1 Represents the cycle-to-cycle residual jitter from the comparator alone. 2 Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The primary limiting factor is the settling time of the PLL multiplier in the reference circuitry. The wake-up time assumes there is no capacitor on DAC BP and that the recommended PLL loop filter values are used. 3 SYSCLK cycle refers to the clock frequency used on-chip to drive the DDS core. This is equal to the frequency of the reference source times the value of the PLL-based reference clock multiplier. 4 SYNC_CLK = ¼ SYSCLK rate. Be sure the high speed sync enable bit, CFR2<11>, is programmed appropriately. 5 This parameter indicates that the digital synchronization feature cannot compensate for phase delays (timing skew) between system clock rising edges. If the system clock edges are aligned, the synchronization function should not increase the skew between the two edges. |
Аналогичный номер детали - AD9954_09 |
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Аналогичное описание - AD9954_09 |
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