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FM93C56EMT8 датащи(PDF) 7 Page - Fairchild Semiconductor |
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FM93C56EMT8 датащи(HTML) 7 Page - Fairchild Semiconductor |
7 / 16 page 7 www.fairchildsemi.com FM93CS56 Rev. C.1 5) Write Disable (WDS) Write Disable (WDS) instruction disables all programming opera- tions and is recommended to follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table1. The device becomes write-disabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WDS instruction. Refer Write Disable cycle diagram. Protect Register Instructions Following five instructions, PRREAD, PREN, PRCLEAR, PRWRITE and PRDS are specific to operations intended for Protect Register. The PRE pin should be held high during these instructions. 1) Protect Register Read (PRREAD) This instruction reads the content of the internal Protect Register. Content of this register is 8-bit wide and is the starting address of the “write-protected” section of the memory array. All memory locations greater than or equal to this address are write-protected. Input information (Start bit, Opcode and Address) for this PRREAD instruction should be issued as listed under Table 1. Upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the Protect Register. This 8-bit data is then shifted out on the DO pin with the MSB first and the LSB last. Like the READ instruction a dummy-bit (logical 0) precedes this 8-bit data output string. Output data changes are initiated on the rising edge of the SK clock. After reading the 8-bit data, the CS signal can be brought low to end the PRREAD cycle. The PRE pin should be held high during this cycle. Refer Protect Register Read cycle diagram. Though the content of this register is 8-bit wide, only the last 7 bits (LSB) are valid for FM93CS56 device. 2) Protect Register Enable (PREN) This instruction is required to enable PRCLEAR, PRWRITE and PRDS instructions and should be executed prior to executing PRCLEAR, PRWRITE and PRDS instructions. However, this PREN instruction is enabled (valid) only the following are true I Device is write-enabled (Refer WEN instruction) I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PREN instruction should be issued as listed under Table1. The Protect Register becomes enabled for PRCLEAR, PRWRITE and PRDS instructions at the end of this cycle when the CS signal is brought low. Note that this PREN instruction must immediately precede a PRCLEAR, PRWRITE or PRDS instruction. In other words, no other instruction should be executed between a PREN instruction and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect Register Enable cycle diagram. 3) Protect Register Clear (PRCLEAR) This instruction clears the content of the Protect register and therefore enables write operations (WRITE or WRALL) to all memory locations. Executing this instruction will program the content of the Protect Register with a pattern of all 1s. However, in this case, WRITE operation to the last memory address (0x01111111) is still enabled. PRCLEAR instruction is enabled (valid) only when the following are true: I PREN instruction was executed immediately prior to PRCLEAR instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRCLEAR instruction should be issued as listed under Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed clear cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal clear cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Protect Register Clear cycle diagram. 4) Protect Register Write (PRWRITE) This instruction is used to write the starting address of the memory section to be write-protected into the Protect register. After the execution of PRWRITE instruction, all memory locations greater than or equal to this address are write-protected. PRWRITE instruction is enabled (valid) only the following are true: I PRCLEAR instruction was executed first (to clear the Protect Register) I PREN instruction was executed immediately prior to PRWRITE instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRWRITE instruction should be issued as listed under Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Protect Register Write cycle diagram. 5) Protect Register Disable (PRDS) Unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the Protect Register and renders it unalterable in the future. This instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. PRDS instruction is enabled (valid) only the following are true: I PREN instruction was executed immediately prior to PRDS instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRDS |
Аналогичный номер детали - FM93C56EMT8 |
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Аналогичное описание - FM93C56EMT8 |
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