поискавой системы для электроныых деталей |
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FM18W08-SG датащи(PDF) 2 Page - Cypress Semiconductor |
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FM18W08-SG датащи(HTML) 2 Page - Cypress Semiconductor |
2 / 12 page FM18W08 Document Number: 001-86207 Rev. ** Page 2 of 12 Address Latch & Decoder A(14:0) CE Control Logic WE A(14:0) I/O Latch Bus Driver OE 32,768 x 8 FRAM Array DQ(7:0) Figure 1. Block Diagram Pin Description Pin Name Type Description A(14:0) Input Address: The 15 address lines select one of 32,768 bytes in the F-RAM array. The address value is latched on the falling edge of /CE. DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the F-RAM array. /CE Input Chip Enable: /CE selects the device when low. Asserting /CE low causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. /OE Input Output Enable: Asserting /OE low causes the FM18W08 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri- stated. /WE Input Write Enable: Asserting /WE low causes the FM18W08 to write the contents of the data bus to the address location latched by the falling edge of /CE. VDD Supply Supply Voltage VSS Supply Ground Functional Truth Table /CE /WE Function H X Standby/Precharge X Latch Address (and Begin Write if /WE=low) L H Read L Write Note: The /OE pin controls only the DQ output buffers. |
Аналогичный номер детали - FM18W08-SG |
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Аналогичное описание - FM18W08-SG |
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