поискавой системы для электроныых деталей |
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AD5326BRUZ-REEL71 датащи(PDF) 6 Page - Analog Devices |
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AD5326BRUZ-REEL71 датащи(HTML) 6 Page - Analog Devices |
6 / 24 page AD5306/AD5316/AD5326 Rev. F | Page 6 of 24 TIMING CHARACTERISTICS1 VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter2 A, B Versions Limit at TMIN, TMAX Unit Conditions/Comments t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD,STA, start/repeated start condition hold time t5 100 ns min tSU,DAT, data setup time t63 0.9 μs max tHD,DAT, data hold time 0 μs min t7 0.6 μs min tSU,STA, setup time for repeated start t8 0.6 μs min tSU,STO, stop condition setup time t9 1.3 μs min tBUF, bus free time between a stop and a start condition t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 250 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1CB4 ns min tF, fall time of SCL and SDA when transmitting t12 20 ns min LDAC pulse width t13 400 ns min SCL rising edge to LDAC rising edge CB4 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. SCL SDA t1 t3 LDAC1 LDAC2 START CONDITION REPEATED START CONDITION STOP CONDITION NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. t4 t6 t5 t7 t8 t2 t13 t4 t11 t10 t12 t12 t9 Figure 2. 2-Wire Serial Interface Timing Diagram |
Аналогичный номер детали - AD5326BRUZ-REEL71 |
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Аналогичное описание - AD5326BRUZ-REEL71 |
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