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AD7304BR-REEL датащи(PDF) 6 Page - Analog Devices |
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AD7304BR-REEL датащи(HTML) 6 Page - Analog Devices |
6 / 20 page AD7304/AD7305 Rev. C | Page 6 of 20 SDI CLK CS LDAC SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tCSH tLD2 tCSS tLD1 SDI CLK CLR LDAC FS ZS VOUT tDS tDH tCL tCH tLDW tS tCLRW tS ±1 LSB ERROR BAND Figure 4. AD7304 General Timing Diagram tSDR SDI/SHDN IDD tSDN Figure 5. AD7304 Timing Diagram Zoom In Table 4. AD7304 Control Logic Truth Table CS 1 CLK1 LDAC CLR1 Serial Shift Register Function Input REG Function DAC Register Function H X H H No effect No effect No effect L ↑+ H H Data advanced 1 bit No effect No effect ↑+ L H H No effect Updated with SR contents2 No effect H X L H No effect Latched with SR contents2 All input register contents transferred3 H X H ↓– No effect Loaded with 0x00 Loaded with 0x00 H X H ↑+ No effect Latched with 0x00 Latched with 0x00 1 ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care. 2 One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1). 3 LDAC is a level-sensitive input. Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format MSB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 LSB B0 AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed in shutdown mode. |
Аналогичный номер детали - AD7304BR-REEL |
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Аналогичное описание - AD7304BR-REEL |
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