LatticeECP3 Architecture

Architecture Overview

LatticeECP3 FPGAs utilize Lattice’s third generation of cost

optimized transceivers and a low-power 65-nm process FPGA

family, LatticeECP3 devices deliver high-performance SERDES

PLLs, DDR3 memory interface, and sysIO buffers. LatticeECP3

provides a low-cost, low-power programmable solution for a

wide variety of wireless and wireline applications.

LatticeECP3 Block Diagram

SERDES SERDES SERDES SERDES

Cascadable

sysDSP Blocks

implements

high-performance

multiplier, MAC,

wide adder

trees, and ALU

functions

efficiently.

JTAG

On-Chip

Oscillator

sysCLOCK PLLs

& DLLs for

clock

management.

sysMEM Embedded Block

RAM (EBR) provides 18kbit

dual port RAM.

Configuration Logic supports

dual boot, encryption and TransFR

updates.

Flexible sysIO

Buffers support

LVCMOS,

HSTL, SSTL,

LVDS and more.

Pre-Engineered Source

Synchronous Support

implements DDR3 at

800Mbps and generic

interfaces up to 1Gbps.

Programmable

Function Unit

(PFU)

perform Logic,

Arithmetic,

Distributed RAM

and Distributed

ROM functions.

Embedded 3.2Gbps SERDES

support PCI Express, Ethernet

(XAUI, 1GbE, SGMII), CPRI,

and 3G/HD/SD-SDI.

Programmable Function

Unit (PFU) Block Diagram

Carry Chain

Carry Chain

LUT4

LUT4

LUT4

FF

FF

LUT4

LUT4

FF

FF

LUT4

LUT4

FF

FF

LUT4

To

Routing

From

Routing

Slice 3

Slice 2

Slice 1

Slice 0

sysDSP Block Diagram

Pipeline

Registers

ALU

Output Registers

Multipliers

Input Registers

Slice 0

Slice 1

==

∑ ± & + ⊕

Pipeline

Registers

ALU

Output Registers

Multipliers

Input Registers

==

∑ ± & + ⊕

sysCLOCK PLL Block Diagram

Internal Feedback

Clock

Input

Reset

Control

Signals

Clock

Feedback

Lock Detect

÷3

Phase

Frequency

Detector /

Voltage

Control

Oscillator

Divider

Duty Trim

Phase/

Duty Cycle/

Duty Trim

17K

33K

67K

92K

149K

6

5

3

4

2

1

0

7

LUTs

UP TO

7Mb

LatticeECP3 EBR SRAM (Mbits)

sysMEM Config Options

Single Port

Dual Port

Pseudo-Dual

Port

16384 x 1

16384 x 1

16384 x 1

8192 x 2

8192 x 2

8192 x 2

4096 x 4

4096 x 4

4096 x 4

2048 x 9

2048 x 9

2048 x 9

1024 x 18

1024 x 18

1024 x 18

512 x 36

—

512 x 36

Dual-boot and 128-bit AES

Encryption

SPI Configuration

Memory

LatticeECP3

Decryption

Engine

128-bit Key

FPGA

Logic

Read

Data

Sector 0

Sector 1

Control

Configuration A

Configuration B

[

[

Pre-Engineered Source

Synchronous Interfaces

DDR3 (800 Mbps)

7:1 LVDS, ADC/DAC

Output Register

Block

(6 Flip/Flops)

ISI

Correction

Input Register

Block

(15 Flip/Flops)

4:1

Gearbox

4:1

Gearbox

FPGA

Fabric

DQS/Strobe Delay & Transition Detect

& Write Clock Generation

Tri-State

Register Block

(2 Flip/Flops)