поискавой системы для электроныых деталей |
|
ADF4106BRUZ датащи(PDF) 10 Page - Analog Devices |
|
ADF4106BRUZ датащи(HTML) 10 Page - Analog Devices |
10 / 24 page ADF4106 Data Sheet Rev. E | Page 10 of 24 GENERAL DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is a normally open switch. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. 100k NC REFIN NC NO SW1 SW2 BUFFER SW3 TO R COUNTER POWER-DOWN CONTROL Figure 17. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 18. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. 500 1.6V 500 AGND RFINA RFINB AVDD BIAS GENERATOR Figure 18. RF Input Stage PRESCALER (P/P +1) The dual-modulus prescaler (P/P + 1), along with the A counter and B counter, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A counter and B counter. The prescaler is programmable. It can be set in soft- ware to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value, and is given by (P2 − P). A COUNTER AND B COUNTER The A counter and B CMOS counter combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 325 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. Pulse Swallow Function The A counter and B counter, in conjunction with the dual- modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is R REFIN f A B P VCO f where: fVCO is the output frequency of the external voltage controlled oscillator (VCO). P is the preset modulus of the dual-modulus prescaler (8/9, 16/17, etc.). B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 6-bit swallow counter (0 to 63). fREFIN is the external reference frequency oscillator. LOAD LOAD FROM RF INPUT STAGE PRESCALER P/P + 1 13-BIT B COUNTER TO PFD 6-BIT A COUNTER N DIVIDER MODULUS CONTROL N = BP + A Figure 19. A and B Counters R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. |
Аналогичный номер детали - ADF4106BRUZ |
|
Аналогичное описание - ADF4106BRUZ |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |