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FW21154AE датащи(PDF) 6 Page - Intel Corporation |
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FW21154AE датащи(HTML) 6 Page - Intel Corporation |
6 / 36 page 6Intel Confidential 21154 PCI-to-PCI Bridge Specification Update Revision History 5/8/01 012 Added information for AE and BE versions of the 21154 product Updated Errata #5 AC Marking state in Table , “Errata” on page 11 Updated status state for Errata #4, #5, #6, and #8 in Table , “Errata” on page 11 and in descriptions in “Errata” on page 15 Updated descriptions for Errata #1 and #3 in Table , “Errata” on page 11 Added last two rows to Table 1, “21154 Markings” on page 14 Updated description for “Tval Timing Issues When Running at 66 MHz for All PCI Signals. Tval timing improved on the 21154BE.” on page 15 Updated description for “Hold Time Issues for All PCI Signals (Both Bused and Control) on the 21154.” on page 16 Added changes #2, #3, and #4 in “Specification Changes” on page 22 Added toTable , “Documentation Changes” on page 13 that include: • “Updated Version of PCI Local Bus Specification” on page 35 • “Section 4.1, Updated s_clk and p_clk description” on page 35 • “Section 4.2, Updated Clock Outputs” on page 35 • “Section 4.4.1, Added Note at End of Section.” on page 35 • “Section 4.5, Table 5 Product Part Numbers have been updated.” on page 36. Note: These documentation changes have been implemented in Version 003 of the 21154 PCI-to-PCI Bridge Hardware Implementation Application Note. 4/30/01 011 The Steppings columns in the “Errata” table, “Specification Changes” table, and “Specification Clarifications” on page 11 were changed to Markings to more accurately reflect the revisions of the component. Errata #3 (Setup Issues With PCI Control Signals When Running at 66 MHz on the 21154BC) of this Specification Update was found to be invalid and is now listed as Fixed. The term “REV_ID6” was removed from the problem section of Errata 3, Setup Issues With PCI Control Signals When Running at 66 MHz on the 21154BC. on page 16. Errata 7, GPIO 66 MHz Timing May Cause Secondary Clocks to be Disabled was added. Errata 8, Bus Conflict Occurs During Configuration on AGP Port of Some Chip Sets. was added. Documentation Changes 12, Section 10.2, Secondary Clock Control, Figure 19, 15, and 18, Section 4.4.1, Serial Clock Mask Shift, Figure 3 were modified, and documentation change 15, Section 10.2.1, Mask and Load Shift Timing Events for 66 MHz Operation was added. 12/15/00 010 Documentation changes 17, 18, and 19, referenced the wrong document number. The correct document number has been updated in the Summary Table of Changes. All references to the 21554 have been changed to 21154. Figures in documentation changes 13 and 20 have been updated. Errata 3 now has stepping C included as an errata in the Summary Table of Changes. 11/13/00 009 Corrected speed settings for 21154AB/AC/BC Markings. 10/02/00 008 Added errata 6. Date Version Description |
Аналогичный номер детали - FW21154AE |
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Аналогичное описание - FW21154AE |
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