TPS3779

TPS3780

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SBVS216B – SEPTEMBER 2012 – REVISED MAY 2013

OUTPUTS (OUT1, OUT2)

In a typical device application, the outputs are connected to a reset or enable input of the processor, such as a

digital signal processor (DSP), central processing unit (CPU), field-programmable gate array (FPGA), or

application-specific integrated circuit (ASIC); or the outputs are connected to the enable input of a voltage

regulator, such as a dc-dc or low-dropout (LDO) regulator.

The TPS3779 provides two push-pull outputs. The logic high level of the outputs is determined by the VCC pin

voltage. With this configuration, pull-up resistors are not required and some board area can be saved. However,

all interface logic levels should be examined. All OUT connections must be compatible with the VCC pin logic

level.

The TPS3780 provides two open-drain outputs (OUT1 and OUT2); pull-up resistors must be used to hold these

lines high when the output goes to a high impedance condition (not asserted). By connecting pull-up resistors to

the proper voltage rails, the outputs can be connected to other devices at correct interface voltage levels. The

outputs can be pulled up to 6.5 V, independent of the device supply voltage. To ensure proper voltage levels,

Characteristics table. By using wired-AND logic, OUT1 and OUT2 can be merged into one logic signal. The

Inputs (SENSE1, SENSE2) section describes how the outputs are asserted or deasserted. Refer to Figure 13 for

a description of the relationship between threshold voltages and the respective output.

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