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ADV212BBCZRL-115 датащи(PDF) 10 Page - Analog Devices |
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ADV212BBCZRL-115 датащи(HTML) 10 Page - Analog Devices |
10 / 44 page ADV212 Rev. B | Page 10 of 44 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter Mnemonic Min Typ Max Unit DREQ Pulse Width DREQPULSE 1 JCLK 1 15 JCLK1 ns DACK Assert to Subsequent DREQ Delay t DREQ 2.5 JCLK1 3.5 × JCLK + 9.01 ns RD to DACK Setup t RDSU 0 ns DACK to Data Valid t RD 2.5 11 ns Data Hold tHD 1.5 ns DACK Assert Pulse Width DACKLOW 2 JCLK1 ns DACK Deassert Pulse Width DACKHIGH 2 JCLK1 ns RD Hold after DACK Deassert t RDHD 0 ns RD Assert to FSRQ Deassert (FIFO Empty) RDFSRQ 1.5 JCLK1 2.5 × JCLK + 9.01 ns DACK to DREQ Deassert (DR × PULS = 0) t DREQRTN 2.5 JCLK1 3.5 × JCLK + 9.01 ns 1 For a definition of JCLK, see Figure 32. RD DACK DREQ HDATA 0 1 2 tRD tHD DREQPULSE tDREQ tRD SU tRD HD DACKHIGH DACKLOW Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000) RD DACK DREQ HDATA 0 1 2 tRD tHD tDREQ RTN tRD SU tRD HD DACKHIGH DACKLOW Figure 10. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) |
Аналогичный номер детали - ADV212BBCZRL-115 |
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Аналогичное описание - ADV212BBCZRL-115 |
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