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AD421BNZ датащи(PDF) 6 Page - Analog Devices |
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AD421BNZ датащи(HTML) 6 Page - Analog Devices |
6 / 14 page AD421 –6– REV. C Table I. FET Characteristics FET Type N-Channel Depletion Mode IDSS 24 mA min BVDS (VLOOP – VCC) min VPINCHOFF VCC max Power Dissipation 24 mA × (VLOOP – VCC) min where VCC is the operating voltage of the AD421 and VLOOP is the loop voltage. The DN25D FET transistor from Supertex 1 meets all the above requirements for the FET. Other suitable transistors include ND2020L and ND2410L, both from Siliconix. There are a number of external components required to com- pensate the regulator loop and ensure stable operation. The capacitor from the VCC pin to the COM pin is required to stabilize the regulator loop. To provide additional compensation for the regulator loop, a compensation capacitor of 0.01 µF should be connected between the COMP and DRIVE pins and an external circuit of a 1 k Ω resistor and a 1000 pF capacitor in series should be connected between DRIVE and COM to stabilize this feed- back loop formed with the regulator op amp and the external pass transistor. DAC Section The AD421 contains a 16-bit sigma-delta DAC to convert the digital information loaded to the input latch into a current. The sigma-delta architecture is particularly useful for the relatively low bandwidth requirements of the industrial control environ- ment because of its inherent monotonicity at high resolution. The AD421 guarantees monotonicity to the 16-bit level. The sigma-delta DAC consists of a second order modulator followed by a continuous time filter. The single bit stream from the modulator controls a switched current source. This current source is then filtered by three resistor-capacitor filter sections. The resistors for each of the filter sections are on-chip while the capacitors are external on the C1–C3 pins. To meet the specified full-scale settling on the part, low dielectric absorption capacitors (NPO) are required. Suitable values for these capacitors are C1 = 0.01 µF, C2 = 0.01 µF, and C3 = 0.0033 µF. Current Amplifier The DAC output current drives the second section, an opera- tional amplifier and NPN transistor which acts as a current amplifier to set the current flowing through the LOOP RTN pin. Figure 4 shows the current amplifier section of the AD421. An 80 k Ω resistor connected between the DAC output and loop return is used as a sampling resistor to determine current. The base drive to the NPN transistor servos the voltage across the 40 Ω resistor to equal the voltage across the 80 kΩ resistor. CIRCUIT DESCRIPTION The AD421 is designed for use in loop-powered 4–20 mA smart transmitter applications. A smart transmitter, as a remote in- strument, controls its current output signal on the same pair of wires from which it receives its power. The AD421 essentially provides three primary functions in the smart transmitter. These functions are a DAC function for converting the microprocessor/ microcontroller’s digital data to analog format, a current amp- lifier which sets the current flowing in the loop and a voltage regulator to provide a stable operating voltage from the loop supply. The part also contains a high speed serial interface, two buffered output references and a clock oscillator circuit. The different sections of the AD421 are discussed in more detail below. Voltage Regulator The voltage regulator consists of an op amp, bandgap reference and an external depletion mode FET pass transistor. This cir- cuit is required to regulate the loop voltage that powers the AD421 itself and the rest of the transmitter circuitry. Figure 3 shows the voltage regulator section of the AD421 plus the associ- ated external circuitry for a VCC of 3.3 V. 1.21V 112.5k 134k 75k 121k VCC LV 2.2 F COM VCC TO EXTERNAL CIRCUITRY DN25D DRIVE COMP 0.01 F 1k 1000pF LOOP(+) BANDGAP REFERENCE AD421 0.01 F Figure 3. AD421 Voltage Regulator Circuit to Provide VCC = 3.3 V The signal on the LV pin selects the voltage to which VCC regulates by changing the gain of the resistor divider between the op amp inverting input and the VCC pin. As the LV pin varies between COM and VCC, the voltage from the regulator loop varies between 3 V and 5 V nominal. With LV connected to COM, the regulated voltage is 5 V; with LV connected through a 0.01 µF capacitor to VCC, the regulated voltage is 3.3 V while if LV is connected to VCC, the regulated voltage is 3 V. The range of loop voltages that can be used by the configuration shown in Figure 3 is determined by the FET breakdown and saturation voltages. The external FET parameters such as Vgs (off), IDSS and transconductance must be chosen so that the op amp output on the DRIVE pin can control the FET operating point while swinging in the range from VCC to COM. The main characteristics for selecting the FET pass transistor are as follows: |
Аналогичный номер детали - AD421BNZ |
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Аналогичное описание - AD421BNZ |
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