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E-L9823013TR датащи(PDF) 7 Page - STMicroelectronics

номер детали E-L9823013TR
подробное описание детали  Octal low-side driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

E-L9823013TR датащи(HTML) 7 Page - STMicroelectronics

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L9823
Block diagram and pins description
18
14
OUT2
Output 2
15
SFPD
The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF. This
feature allows control of incandescent loads where in-rush currents exceed the device's
analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will
instantly shutdown upon sensing an output short or remain ON in a current limiting mode of
operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is
tied to VDD the L9823 output(s) will remain ON in a current limited mode of operation upon
encountering a load short to supply. If the SFPD pin is grounded, a short circuit will
immediately shutdown only the output affected. Other outputs not having a fault condition will
operate normally.
16
VDD
VDD
17
GND
GND
18
GND
GND
19
GND
GND
20
GND
GND
21
N.C.
Not Connected
22
RESET
The Reset pin is active low and used to clear the SPI shift register and in doing so sets all
output switches OFF. With the device in a system with an MCU; upon initial system power up,
the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF
until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset,
the MCU is ready to assert system control with all output switches initially OFF. The Reset pin
is active low and has an internal pull-down incorporated to ensure operational predictability
should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe
and easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low
state for a duration of at least 160ns to ensure reliable Reset.
23
OUT1
Output 1
24
OUT0
Output 0
Table 2. Pins description (continued)
N#
Pin
Description


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