AD783

REV. A

–5–

DEFINITIONS OF SPECIFICATIONS

Acquisition Time—The length of time that the SHA must

remain in the sample mode in order to acquire a full-scale input

step to a given level of accuracy.

Small Signal Bandwidth—The frequency at which the held

output amplitude is 3 dB below the input amplitude, under an

input condition of a 100 mV p-p sine wave.

Full Power Bandwidth—The frequency at which the held

output amplitude is 3 dB below the input amplitude, under an

input condition of a 5 V p-p sine wave.

Effective Aperture Delay—The difference between the switch

delay and the analog delay of the SHA channel. A negative

number indicates that the analog portion of the overall delay is

greater than the switch portion. This effective delay represents

the point in time, relative to the hold command, that the input

signal will be sampled.

Aperture Jitter—The variations in aperture delay for

successive samples. Aperture jitter puts an upper limit on the

maximum frequency that can be accurately sampled.

Hold Settling Time—The time required for the output to

settle to within a specified level of accuracy of its final held value

after the hold command has been given.

Droop Rate—The drift in output voltage while in the hold

mode.

Feedthrough—The attenuated version of a changing input

signal that appears at the output when the SHA is in the hold

mode.

Hold Mode Offset—The difference between the input signal

and the held output. This offset term applies only in the hold

mode and includes the error caused by charge injection and all

other internal offsets. It is specified for an input of 0 V.

Sample Mode Offset—The difference between the input and

output signals when the SHA is in the sample mode.

Nonlinearity—The deviation from a straight line on a plot of

input vs. (held) output as referenced to a straight line drawn

between endpoints, over an input range of –2.5 V and +2.5 V.

Gain Error—Deviation from a gain of +1 on the transfer

function of input vs. held output.

Power Supply Rejection Ratio—A measure of change in the

held output voltage for a specified change in the positive or

negative supply.

Sampled DC Uncertainty—The internal rms SHA noise that

is sampled onto the hold capacitor.

Hold Mode Noise—The rms noise at the output of the SHA

while in the hold mode, specified over a given bandwidth.

Total Output Noise—The total rms noise that is seen at the

output of the SHA while in the hold mode. It is the rms

summation of the sampled dc uncertainty and the hold mode

noise.

Output Drive Current—The maximum current the SHA can

source (or sink) while maintaining a change in hold mode offset

of less than 2.5 mV.

Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is

the ratio of the rms value of the measured input signal to the

rms sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc. The value for

S/N+D is expressed in decibels.

Total Harmonic Distortion (THD)—THD is the ratio of the

rms sum of the first six harmonic components to the rms value

of the measured input signal and is expressed in decibels.

Intermodulation Distortion (IMD)—With inputs consisting

of sine waves at two frequencies, fa and fb, any device with

nonlinearities will create distortion products, of order (m+n), at

sum and difference frequency of mfa

±nfb, where m, n = 0, 1, 2,

3. . . . Intermodulation terms are those for which m or n is not

equal to zero. For example, the second order terms are (fa+fb)

and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),

(fa+2fb) and (fa–2fb). The IMD products are expressed as the

decibel ratio of the rms sum of the measured input signals to the

rms sum of the distortion terms. The two signals are of equal

amplitude, and peak value of their sums is –0.5 dB from full

scale. The IMD products are normalized to a 0 dB input signal.

FUNCTIONAL DESCRIPTION

The AD783 is a complete, high speed sample-and-hold

amplifier that provides high speed sampling to 12-bit accuracy

in 250 ns.

The AD783 is completely self-contained, including an on-chip

hold capacitor, and requires no external components or adjust-

ments to perform the sampling function. Both input and output

are treated as a single-ended signal, referred to common.

The AD783 utilizes a proprietary circuit design which includes a

self-correcting architecture. This sample-and-hold circuit

corrects for internal errors after the hold command has been

given, by compensating for amplifier gain and offset errors, and

charge injection errors. Due to the nature of the design, the

SHA output in the sample mode is not intended to provide an

accurate representation of the input. However, in hold mode,

the internal circuitry is reconfigured to produce an accurately

held version of the input signal. Below is a block diagram of the

AD783.

1

2

3

45

6

7

8

AD783

IN

COMMON

NC

OUT

S/H

NC

NC = NO CONNECT

X1

Functional Block Diagram