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UC1860 датащи(PDF) 8 Page - Texas Instruments |
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UC1860 датащи(HTML) 8 Page - Texas Instruments |
8 / 10 page UC1860 UC2860 UC3860 OUTPUT STAGE The two totem pole output stages can be programmed by Mode to operate alternately or in unison. When Mode is low the outputs alternate. During UVLO, the outputs are low. Extreme care needs to be exercised in the application of these outputs. Each output can source and sink transient currents of 2A or more and is designed for high values of dl/dt. This dictates the use of a ground plane, shielded in- terconnect cables, Schottky diode clamps from the output pins to Pwr Gnd (power ground), and some series resis- tance to provide damping. Pwr Gnd should not exceed ±0.2V from signal ground. BYPASS NOTE The reference should be bypassed with a 0.1 µF ceramic capacitor from the VREF pin directly to the ground plane near the Signal Ground pin. The timing capacitors on CVFO and RC should be treated likewise. VCC, however, should be bypassed with a ceramic capacitor from the VCC pin to the section of ground plane that is connected to Power Ground. Any required bulk reservoir capacitor should parallel this one. The two ground plane sections can then be joined at a single point to optimize noise re- jection and minimize DC drops. Output Saturation Voltage vs Load Current Output Saturation Voltage vs Load Current Output Rise & Fall Time vs Load Capacitance UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 603-424-2410 • FAX 603-424-3460 8 |
Аналогичный номер детали - UC1860 |
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Аналогичное описание - UC1860 |
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